• The Transactions of the Korea Information Processing Society
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• v.5 no.1
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• pp.24-32
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• 1998

The bus contention among bus-based shared-memory multiprocessors limits their performance. In addition, under split bus transaction environment, multiprocessors may make some memory requests unnecessary stand by in the memory access buffer, which makes system performance worse. This unnecessary stand-by can be eliminated by maintaining the bitmap table which contains the status bit for each memory block. However, this mechanism requires a great size of SRAM for the status information, which is fully mapped from the whole memory blocks. To solve this problem, we propose a bitmap cache which exploits partial mapping and locality of references. The simulation results show that the proposed system can greatly reduce the capacity of SRAM for the status information with little deteriorating its performance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.4 s.334
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• pp.19-28
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• 2005

In this paper, we proposed a parallel fast 2-D discrete wavelet transform hardware architecture based on lifting scheme. The proposed architecture improved the 2-D processing speed, and reduced internal memory buffer size. The previous lifting scheme based parallel 2-D wavelet transform architectures were consisted with row direction and column direction modules, which were pair of prediction and update filter module. In 2-D wavelet transform, column direction processing used the row direction results, which were not generated in column direction order but in row direction order, so most hardware architecture need internal buffer memory. The proposed architecture focused on the reducing of the internal memory buffer size and the total calculation time. Reducing the total calculation time, we proposed a 4-way data flow scheduling and memory based parallel hardware architecture. The 4-way data flow scheduling can increase the row direction parallel performance, and reduced the initial latency of starting of the row direction calculation. In this hardware architecture, the internal buffer memory didn't used to store the results of the row direction calculation, while it contained intermediate values of column direction calculation. This method is very effective in column direction processing, because the input data of column direction were not generated in column direction order The proposed architecture was implemented with VHDL and Altera Stratix device. The implementation results showed overall calculation time reduced from $N^2/2+\alpha$ to $N^2/4+\beta$, and internal buffer memory size reduced by around $50\%$ of previous works.

• Journal of KIISE:Computing Practices and Letters
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• v.9 no.1
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• pp.13-24
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• 2003

MPEG-4 is a standard for multimedia applications and provides a set of technologies to satisfy the needs of authors, service providers and end users alike. In this paper, we suggest a Real-time Multiple Circular Buffer (M4RM Buffer) model, which is suitable for streaming these MPEG-4 contents efficiently. M4RM buffer generates each structure of the buffer, which matches well with each object composing an MPEG-4 content, according to the transferred information, and manipulates multiple read/write operations only by its reference. It divides the decoder buffer and the composition buffer, which are described in the standard, by the unit of frame allocated to minimize the range of access. This buffer unit of a frame is allocated according to the object description. Also, it processes the objects synchronization within the buffer and provides APIs for an efficient buffer management to process the real-time user events. Based on the performance evaluation, we show that M4RM buffer model decreases the waiting time in a buffer frame, and so allows the real-time streaming of an MPEG-4 content using the smaller size of the memory block than IM1-2D and Window Media Player.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.4
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• pp.1-5
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• 2011

We present the implementation of MAC system for MBOA UWB SoC. The implemented MBOA MAC algorithm is not master control mechanism, but distributed network mechanism. Therefore, mesh network can be easily constructed because MAC consists of distributed network and administrates network. The ARM926EJ with cache is adopted for high performnace and AMBA bus is applied for system design and reuse. In addition, the system operating clock management algorithm is implemented for low power consumption. The dedicated DMA for MAC is designed between the system memory buffer and MAC hardware, and the dedicated DMA for USB 2.0 is also implemented between system memory buffer and host for high data transaction.

• The KIPS Transactions:PartD
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• v.16D no.6
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• pp.825-834
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• 2009

최근에 낸드 플래시 메모리는 빠른 접근속도, 저 전력 소모, 높은 내구성 등의 특성으로 인하여 차세대 대용량 저장 매체로 각광 받고 있다. 그러나 디스크 기반의 저장 장치와는 달리 비대칭적인 읽기, 쓰기, 소거 연산의 처리 속도를 가지고 있고 제자리 갱신이 불가능한 특성을 가지고 있다. 따라서 디스크 기반 시스템의 버퍼 교체 정책은 플래시 메모리 기반의 시스템에서 좋은 성능을 보이지 않을 수 있다. 이러한 문제를 해결하기 위해 플래시 메모리의 특성을 고려한 새로운 플래시 메모리 기반의 버퍼 교체 정책이 제안되어 왔다. 본 논문에서는 디스크 기반의 저장 장치에서 우수한 성능을 보인 CLOCK-Pro를 낸드 플래시 메모리의 특성을 고려하여 개선한 CLOCK-NAND를 제안한다. CLOCK-NAND는 CLOCK-Pro의 알고리즘에 기반하며, 추가적으로 페이지 접근 정보를 효율적으로 활용하기 위한 새로운 핫 페이지 변경을 한다. 또한, 더티인 핫 페이지에 대해 콜드 변경 지연 정책을 사용하여 쓰기 연산을 지연하며, 이러한 새로운 정책들로 인하여 낸드 플래시 메모리에서 쓰기 연산 횟수를 효율적으로 줄이는 우수한 성능을 보인다.

• Journal of the Korea Society of Computer and Information
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• v.14 no.4
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• pp.9-17
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• 2009

In this paper, we propose a dynamic load distribution technique at the operating system level in mobile storage systems with a heterogeneous storage pair of a small form-factor and disk and a flash memory, which aims at saving energy consumption as well as enhancing I/O performance. Our proposed technique takes a combinatory approach of file placement and buffer cache management techniques to find how the load can be distributed in an energy and performance-aware way for a heterogeneous mobile storage air of a hard disk and a flash memory. We demonstrate that the proposed technique provides better experimental results with heterogeneous mobile storage devices compared with the existing techniques through extensive simulations.

• The Journal of the Korea Contents Association
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• v.18 no.3
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• pp.34-40
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• 2018

In this study, the optimal buffer size is calculated for seamless video playback on a mobile device. Buffer means the memory space for multimedia packet which arrives in mobile device for video play such as VOD service. If the buffer size is too large, latency time before video playback can be longer. However, if it is too short, playback service can be paused because of shortage of packets arrived. Hence, the optimal buffer size insures QoS of video playback on mobile devices. We model the process of buffering into a discret-time queueing model. Mean busy period length and mean waiting time of Geo/G/1 queue with N-policy is analyzed. After then, we uses the main performance measures to present numerical examples to decide the optimal buffer size on mobile devices. Our results enhance the user satisfaction by insuring the seamless playback and minimizing the initial delay time in VOD streaming process.

• KIPS Transactions on Computer and Communication Systems
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• v.6 no.6
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• pp.255-260
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• 2017

The limitation of real-time video conferencing system is that the delay of network and buffering and the transmission of user information are not efficiently performed between systems, so real - time performance is not guaranteed completely. In order to overcome this problem, the study on the extension of the network infrastructure and the jitter delay is actively carried out, but the study on the buffering delay is insufficient. In this paper, we propose a frame-rate control buffer management (FRCB) scheme to solve the problem caused by buffering delay. The FRCB is used to prevent overflow and underflow of the buffer by adopting the two-stage buffer threshold of Fast-play THreshold (FTH) and Slow-play THreshold (STH). Therefore, it showed better performance than jitter buffer even under high CPU load, and showed that it is suitable for high quality real time video conferencing.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.1
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• pp.36-42
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• 2016

In multi-level-cell based storage devices, TLC NAND has been employed solid state drive due to cost effectiveness. Since TLC has slow performance and low endurance compared with MLC, TLC based storage has adopted SLC buffer scheme to improve performance. To improve SLC buffer scheme, this paper proposes page overwriting method in SLC block. This method provides data updates without erase operation within a limited number. When SLC buffer area is filled up, FTL should execute copying valid pages and erasing it. The proposed method reduces erase counts by 50% or more compared with previous SLC buffer scheme. Simulation results show that the proposed SLC buffer overwrite method achieves 2 times write performance improvement.

• International Journal of Computer Science & Network Security
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• v.23 no.1
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• pp.153-163
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• 2023

This study is situated in the context of intelligent transport systems, where in-vehicle devices assist drivers to avoid accidents and therefore improve road safety. The vehicles present in a given area form an ad' hoc network of vehicles called vehicular ad' hoc network. In this type of network, the nodes are mobile vehicles and the messages exchanged are messages to warn about obstacles that may hinder the correct driving. Node mobilities make it impossible for inter-node communication to be end-to-end. Recognizing this characteristic has led to delay-tolerant vehicular networks. Embedded devices have small buffers (memory) to hold messages that a node needs to transmit when no other node is within its visibility range for transmission. The performance of a vehicular delay-tolerant network is closely tied to the successful management of the nodes' transit buffer. In this paper, we propose a message transit buffer management model for nodes in vehicular delay tolerant networks. This model consists in setting up, on the one hand, a policy of dropping messages from the buffer when the buffer is full and must receive a new message. This drop policy is based on the concept of intermediate node to destination, queues and priority class of service. It is also based on the properties of the message (size, weight, number of hops, number of replications, remaining time-to-live, etc.). On the other hand, the model defines the policy for selecting the message to be transmitted. The proposed model was evaluated with the ONE opportunistic network simulator based on a 4000m x 4000m area of downtown Bouaké in Côte d'Ivoire. The map data were imported using the Open Street Map tool. The results obtained show that our model improves the delivery ratio of security alert messages, reduces their delivery delay and network overload compared to the existing model. This improvement in communication within a network of vehicles can contribute to the improvement of road safety.