• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.6B
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• pp.1183-1190
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• 1999

This paper presents an efficient hardware architecture to improve the frame memory interface occupying the largest hardware area together with motion estimator in implementing MPEG-2 video encoder as an ASIC chip. In this architecture, the memory size for internal data buffering and hardware area for frame memory interface control logic are reduced through the efficient memory map organization of the external SDRAM having dual bank and memory access timing optimization between the video encoder and external SDRAM. In this design, 0.5 m, CMOS, TLM (Triple Layer Metal) standard cells are used as design libraries and VHDL simulator and logic synthesis tools are used for hardware design add verification. The hardware emulator modeled by C-language is exploited for various test vector generation and functional verification. The architecture of the improved frame memory interface occupies about 58% less hardware area than the existing architecture[2-3], and it results in the total hardware area reduction up to 24.3%. Thus, the (act that the frame memory interface influences on the whole area of the video encoder severely is presented as a result.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.473-482
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• 2017

Hand gesture recognition is regarded as new Human Computer Interaction (HCI) technologies for the next generation of mobile devices. Previous hand gesture implementation requires a large memory and computation power for hand segmentation, which fails to give real-time interaction with mobile devices to users. Therefore, in this paper, we presents a low latency and memory-efficient hand segmentation architecture for natural hand gesture recognition. To obtain both high memory-efficiency and low latency, we propose a streaming hand contour tracing unit and a fast contour filling unit. As a result, it achieves 7.14 ms latency with only 34.8 KB on-chip memory, which are 1.65 times less latency and 1.68 times less on-chip memory, respectively, compare to the best-in-class.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.360-363
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• 1999

Video data compression is a major key technology in the field of multimedia applications. Variable-length coding is the most popular data compression technique which has been used in many data compression standards, such as JPEG, MPEG and image data compression standards, etc. In this paper, we present memory efficient VLC decoder architecture for MPEG-2 application which can achieve small memory space and higher throughput. To reduce the memory size, we propose a new grouping, remainder generation method and merged lookup table (LUT) for variable length decoders (VLD's). In the MPEG-2, the discrete cosine transform (DCT) coefficient table zero and one are mapped onto one memory whose space requirement has been minimized by using efficient memory mapping strategy The proposed memory size is only 256 words in spite of mapping two DCT coefficient tables.

• Korean Institute of Interior Design Journal
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• v.15 no.6 s.59
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• pp.43-51
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• 2006

The purpose of this study is to present possibility about applying space design of urban theory focused on collective memory. Urban which is the final data of human's collective life has been recognized creative circumstances human collective is living. It can not think without collective from its motivation to problem of form as well as building as element which compose these cities. It is to recognize essential attribute of construction in the collective that think architecture with urban, and It means that recognize actuality of architecture that can talk as the most collective product that represent human. There was discussion for collective and urban. But, this problem was proceeded to clear human knowledge of architecture mainly in other discipline, and even if speak as field of architecture, it could just pass confined meaning by refering at process that clear several main aspects of architecture as doing not pass over more than it. Problem of form that is ultimate aspect of architecture remained by different thing still doing not combine with collective architecture, and occasionally happened the case that make collective of architecture and relation of form overly incommodiously reducing form by a tool for diagram, shape, figuration in the aspect of collective. This research study concept for memory collective in the urban and collective of architecture, and choose urban planning methodology and their work by specific example between Aldo Rosi and Rem Koolhaas dealing with architecture and urban, and present possibility about space design of urban.

• Smart Structures and Systems
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• v.19 no.4
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• pp.341-350
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• 2017

Based on the super elastic properties of the shape memory alloy (SMA) and the inverse piezoelectric effect of piezoelectric (PZT) ceramics, a kind of hybrid semi-active control device was designed and made, its mechanical properties test was done under different frequency and different voltage. The local search ability of genetic algorithm is poor, which would fall into the defect of prematurity easily. A kind of adaptive immune memory cloning algorithm(AIMCA) was proposed based on the simulation of clone selection and immune memory process. It can adjust the mutation probability and clone scale adaptively through the way of introducing memory cell and antibody incentive degrees. And performance indicator based on the modal controllable degree was taken as antigen-antibody affinity function, the optimization analysis of damper layout in a space truss structure was done. The structural seismic response was analyzed by applying the neural network prediction model and T-S fuzzy logic. Results show that SMA and PZT friction composite damper has a good energy dissipation capacity and stable performance, the bigger voltage, the better energy dissipation ability. Compared with genetic algorithm, the adaptive immune memory clone algorithm overcomes the problem of prematurity effectively. Besides, it has stronger global searching ability, better population diversity and faster convergence speed, makes the damper has a better arrangement position in structural dampers optimization leading to the better damping effect.

• Journal of the Semiconductor & Display Technology
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• v.22 no.3
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• pp.78-83
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• 2023

This paper proposes a lightweight trace-driven Processing-In-Memory (PIM) simulator, TP-Sim. TP-Sim is a General Purpose PIM (GP-PIM) simulator that evaluates various PIM system performance-related metrics. Based on instruction and memory traces extracted from the Intel Pin tool, TP-Sim can replay trace files for multiple models of PIM architectures to compare its performance. To verify the availability of TP-Sim, we estimated three different system configurations on the STREAM benchmark. Compared to the traditional Host CPU-only systems with conventional memory hierarchy, simple GP-PIM architecture achieved better performance; even the Host CPU has the same number of in-order cores. For further study, we also extend TP-Sim as a part of a heterogeneous system simulator that contains CPU, GPGPU, and PIM as its primary and co-processors.

• ETRI Journal
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• v.44 no.6
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• pp.1020-1033
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• 2022

In this paper, we propose novel disaggregated memory module (dMM) architecture and memory access control schemes to solve the collision and contention problems of memory disaggregation, reducing the average memory access time to less than 1 ㎲. In the schemes, the distributed scheduler in each dMM determines the order of memory read/write access based on delay-sensitive priority requests in the disaggregated memory access frame (dMAF). We used the memory-intensive first (MIF) algorithm and priority-based MIF (p-MIF) algorithm that prioritize delay-sensitive and/or memory-intensive (MI) traffic over CPU-intensive (CI) traffic. We evaluated the performance of the proposed schemes through simulation using OPNET and hardware implementation. Our results showed that when the offered load was below 0.7 and the payload of dMAF was 256 bytes, the average round trip time (RTT) was the lowest, ~0.676 ㎲. The dMM scheduling algorithms, MIF and p-MIF, achieved delay less than 1 ㎲ for all MI traffic with less than 10% of transmission overhead.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1767-1770
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• 2003

This paper proposes an efficient network architecture for reflective memory system (RMS). Using this architecture, the time for broadcasting a shared-data to all nodes can be significantly shortened. The device named topology conversion switch (TCS) is implemented to realize the network architecture. The implemented TCS is applied to the ethernet based real time control network (ERCnet) to evaluate the performance.

• The Transactions of the Korea Information Processing Society
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• v.5 no.10
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• pp.2686-2703
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• 1998

The widening pClformnnce gap between processor and memory causes an emergence of the promising architecture, processor-memory (PM) integration In this paper, various design issues for P-M integration are studied, First, an analytical model of the DRAM access time is constructed considering both the bank conflict ratio and the DRAM page hit ratio. Then the points of both the performance improvement and the perfonnance bottle neck are found by the proposed model as designing on-chip DRAM architectures. This paper proposes the new architecture, called the delayed precharge bank architecture, to improve the perfonnance of memory system as increasing the DRAM page hit ratio. This paper also adapts an efficient bank interleaving mechanism to the proposed architecture. This architecture is verified !II he better than the hierarchical multi-bank architecture as well as the conventional bank architecture by executiun driven simulation. Eight SPEC95 benchmarks are used for simulation as changing parameters for the cache architecture, the number of DRAM banks, and the delayed time quantum.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.101-109
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• 2009

Generally, depth cache and pixel cache of 3D graphics are designed by using write-back scheme for efficient use of memory bandwidth. Also, there are write after read operations of same address or only write operations are occurred frequently in 3D graphics cache. If a cache miss is detected, an access to the external memory for write back operation and another access to the memory for handling the cache miss are operated simultaneously. So on frequent cache miss situations, as the memory access bandwidth limited, the access time of the external memory will be increased due to memory bottleneck problem. As a result, the total performance of the processor or the IP will be decreased, also the problem will increase peak power consumption. So in this paper, we proposed a novel early write back cache architecture so as to solve the problems issued above. The proposed architecture controls the point when to access the external memory as to copy the valid data block. And this architecture can improve the cache performance with same hit ratio and same capacity cache. As a result, the proposed architecture can solve the memory bottleneck problem by preventing intensive memory accesses. We have evaluated the new proposed architecture on 3D graphics z cache and pixel cache on a SoC environment where ARM11, 3D graphic accelerator and various IPs are embedded. The simulation results indicated that there were maximum 75% of performance increase when using various simulation vectors.