• 제목/요약/키워드: Matching Efficiency

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Broadband Impedance Matching Circuit Design for PLC Coupler Using Tchebycheff Equalizer

  • Kim, Gi-Rae;Tangyao, Xie
    • Journal of information and communication convergence engineering
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    • 제7권2호
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    • pp.113-118
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    • 2009
  • This paper is about design broadband impedance matching circuit for Coupler to improve power transfer efficiency in the power line communication (PLC) system. The Tchebycheff gain function algorithm is represented to design broadband matching circuit. A practical PLC Coupler impedance matching circuit is designed, and the characteristics for S11 and S21 of PLC coupler are enhanced comparing with unmatched one. This is done by maximizing the power transfer gain from modem to the load.

Design of Broadband Impedance Matching Circuit for PLC Coupler using Butterworth Equalizer

  • Xie, Tangyao;Kim, Gi-Rae
    • Journal of information and communication convergence engineering
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    • 제8권3호
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    • pp.258-262
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    • 2010
  • This paper represents design broadband impedance matching circuit for Coupler to improve power transfer efficiency in the broadband power line communication(BPLC) systems. The Butterworth gain function equalizer is used to design broadband matching circuit. A practical PLC Coupler impedance matching circuit is designed, and the characteristics for S11 and S21 of PLC Coupler are enhanced comparing with unmatched one. This is done by maximizing the power transfer gain from modem to the load.

An Energy-Efficient Matching Accelerator Using Matching Prediction for Mobile Object Recognition

  • Choi, Seongrim;Lee, Hwanyong;Nam, Byeong-Gyu
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제16권2호
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    • pp.251-254
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    • 2016
  • An energy-efficient object matching accelerator is proposed for mobile object recognition based on matching prediction scheme. Conventionally, vocabulary tree has been used to save the external memory bandwidth in object matching process but involved massive internal memory transactions to examine each object in a database. In this paper, a novel object matching accelerator is proposed based on matching predictions to reduce unnecessary internal memory transactions by mitigating non-target object examinations, thereby improving the energy-efficiency. Experimental results show a 26% reduction in power-delay product compared to the prior art.

A Fast Image Matching Method for Oblique Video Captured with UAV Platform

  • Byun, Young Gi;Kim, Dae Sung
    • 한국측량학회지
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    • 제38권2호
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    • pp.165-172
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    • 2020
  • There is growing interest in Vision-based video image matching owing to the constantly developing technology of unmanned-based systems. The purpose of this paper is the development of a fast and effective matching technique for the UAV oblique video image. We first extracted initial matching points using NCC (Normalized Cross-Correlation) algorithm and improved the computational efficiency of NCC algorithm using integral image. Furthermore, we developed a triangulation-based outlier removal algorithm to extract more robust matching points among the initial matching points. In order to evaluate the performance of the propose method, our method was quantitatively compared with existing image matching approaches. Experimental results demonstrated that the proposed method can process 2.57 frames per second for video image matching and is up to 4 times faster than existing methods. The proposed method therefore has a good potential for the various video-based applications that requires image matching as a pre-processing.

화질 추정과 특징점 분류를 이용한 Delaunay 삼각화 기반의 지문 정합 알고리즘 (Delaunay Triangulation based Fingerprint Matching Algorithm using Quality Estimation and Minutiae Classification)

  • 성영진;김경환
    • 한국멀티미디어학회논문지
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    • 제13권4호
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    • pp.547-559
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    • 2010
  • Delaunay 삼각화는 회전과 평행 이동에 강건하여 지문 인식에 적합하다. 그러나 특징점이 소실되거나 추가로 추출되는 경우 지문 인식 성능이 저하되고 계산 복잡도가 증가하게 된다. 본 논문에서는 지문 영상의 지역적 화질 척도 분석을 통해 저화질 영역을 설정하고, 추출된 특징점을 4개의 그룹으로 분류하여 정합과정에 이용함으로써 인식 성능을 개선하고 계산 복잡도를 감소시켰다. 정합 후보 영역에서의 저화질 영역 제거와 특징점 분류에 대한 실험을 통해 성능의 저하 없이 정합 소요 시간이 감소되는 것을 확인하였고, NIST에서 제공하는 정합 알고리즘 (BOZORTH3)보다 정합 성능이 향상되었음을 확인하였다.

GPU를 이용한 보다 빠른 지문 인식 알고리즘 (Faster Fingerprint Matching Algorithm Using GPU)

  • 리아즈 시드라;이상웅
    • 한국멀티미디어학회:학술대회논문집
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    • 한국멀티미디어학회 2012년도 춘계학술발표대회논문집
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    • pp.43-45
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    • 2012
  • This paper is based on embedding the biometrics techniques on GPU for better computational efficiency and fast matching process using the parallel nature of the GPU processors to compare thousands of images for fingerprint recognition in a fraction of a second. In this paper we worked on GPU (INVIDIA GeForce GTX 260 with compute capability 1.3 and dual core-2-dou processor) for fingerprint matching and found that the efficiency is better than the results with related work already done on CMOS, CPU, ARM9, MATLAB Neural Networks etc which shows the better performance of our system in terms of computational time. The features matching process proposed for fingerprint recognition and the verification procedure is done on 5,000 images which are available online in the databases FVC2000, 2002, 2004 [1].

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A NEW LANDSAT IMAGE CO-REGISTRATION AND OUTLIER REMOVAL TECHNIQUES

  • Kim, Jong-Hong;Heo, Joon;Sohn, Hong-Gyoo
    • 대한원격탐사학회:학술대회논문집
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    • 대한원격탐사학회 2006년도 Proceedings of ISRS 2006 PORSEC Volume II
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    • pp.594-597
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    • 2006
  • Image co-registration is the process of overlaying two images of the same scene. One of which is a reference image, while the other (sensed image) is geometrically transformed to the one. Numerous methods were developed for the automated image co-registration and it is known as a time-consuming and/or computation-intensive procedure. In order to improve efficiency and effectiveness of the co-registration of satellite imagery, this paper proposes a pre-qualified area matching, which is composed of feature extraction with Laplacian filter and area matching algorithm using correlation coefficient. Moreover, to improve the accuracy of co-registration, the outliers in the initial matching point should be removed. For this, two outlier detection techniques of studentized residual and modified RANSAC algorithm are used in this study. Three pairs of Landsat images were used for performance test, and the results were compared and evaluated in terms of robustness and efficiency.

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A New Landsat Image Co-Registration and Outlier Removal Techniques

  • Kim, Jong-Hong;Heo, Joon;Sohn, Hong-Gyoo
    • 대한원격탐사학회지
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    • 제22권5호
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    • pp.439-443
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    • 2006
  • Image co-registration is the process of overlaying two images of the same scene. One of which is a reference image, while the other (sensed image) is geometrically transformed to the one. Numerous methods were developed for the automated image co-registration and it is known as a timeconsuming and/or computation-intensive procedure. In order to improve efficiency and effectiveness of the co-registration of satellite imagery, this paper proposes a pre-qualified area matching, which is composed of feature extraction with Laplacian filter and area matching algorithm using correlation coefficient. Moreover, to improve the accuracy of co-registration, the outliers in the initial matching point should be removed. For this, two outlier detection techniques of studentized residual and modified RANSAC algorithm are used in this study. Three pairs of Landsat images were used for performance test, and the results were compared and evaluated in terms of robustness and efficiency.

가변 임피던스 매칭 네트워크를 이용한 영상 감시 Disposable IoT용 광대역 CMOS RF 에너지 하베스터 (A CMOS Wideband RF Energy Harvester Employing Tunable Impedance Matching Network for Video Surveillance Disposable IoT Applications)

  • 이동구;이두희;권구덕
    • 전기학회논문지
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    • 제68권2호
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    • pp.304-309
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    • 2019
  • This paper presents a CMOS RF-to-DC converter for video surveillance disposable IoT applications. It widely harvests RF energy of 3G/4G cellular low-band frequency range by employing a tunable impedance matching network. The proposed converter consists of the differential-drive cross-coupled rectifier and the matching network with a 4-bit capacitor array. The proposed converter is designed using 130-nm standard CMOS process. The designed energy harvester can rectify the RF signals from 700 MHz to 900 MHz. It has a peak RF-to-DC conversion efficiency of 72.25%, 64.97%, and 66.28% at 700 MHz, 800 MHz, and 900 MHz with a load resistance of 10kΩ, respectively.

정합회로 장착 고효율 소형안테나의 해석 (Analysis of High Efficiency Small Antenna with Matching Circuit)

  • 황재호
    • 한국정보통신학회논문지
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    • 제16권7호
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    • pp.1358-1363
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    • 2012
  • 본 논문에서는 초전도체 안테나와 같은 고효율 소형안테나를 해석하고 있다. 그런데 초전도체의 표면저항은 주파수의 제곱에 비례하여 증가하기 때문에 초전도체 안테나는 낮은 주파수대역에서 유용하다. 따라서 이에 사용되는 안테나의 크기가 커지게 되는데 이와 같은 안테나를 소형화 하는데 있어 정합회로의 역할은 매우 중요하다 할 수 있다. 본 논문은 초전도체 소형안테나를 구성함에 있어 손실특성을 최소화 할 수 있는 최적의 정합회로 구조를 준정근사법을 이용하여 해석한다. 또한 결과의 유효성을 확인하기 위해 안테나의 입력임피던스특성과 방사특성을 평가한다.