• Journal of IKEEE
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• 제17권4호
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• pp.537-543
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• 2013

This paper proposed a low EMI spread spectrum clock generator (SSCG) using discontinuous frequency modulation technique. The proposed SSCG is designed for triangular frequency modulation with high modulation depth. When the maximum time interval error (MTIE) of the SSCG is higher than given limit, the output frequency of SSCG is divided by two and used for reducing the time interval error (TIE). This discontinuous frequency modulation technique can effectively reduce the EMI within given limit. The simulated EMI of proposed SSCG was reduced by 18.5dB than that of conventional methods.

• Journal of the Institute of Convergence Signal Processing
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• 제3권2호
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• pp.45-52
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• 2002

EMI(Electromagnetic Interface) is a measure of electomagnetic radiation from equipment in the range of 10KHz to 3GHz, and can cause unexpected reactions of electronics/electrical equipment. In this study, for safe and stable communication operation, a STGU(System Timing Genetation Unit), which is a 2.5Gbps SDH System and a major EMI source, was employed to simulate electromagnetic interface. In On-Site test, the power of fundamental frequency of EMI of interest and its harmonics were measured. Also, a low pass filter at cut-off frequency of 2GHz was specifically designed to minimize the effect of EMI between electronic components. When the low pass filter was implemented within the STGU, the power of EMI decreased more than 20dBm. Finally, when TIE and MTIE, two important quality measure in synchronous reference clcok, was assessed, ITU-T G8l3 requirements are satisfied.

• Journal of the Institute of Convergence Signal Processing
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• 제15권4호
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• pp.169-175
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• 2014

NG-SDH system is connected with networks throughout optical fibers. Network synchronization controller is a necessary for the data synchronization in each optical transmission system. In this paper, we have design and implementation the network synchronization controller using SOPC(system on a programmable chip) design technic. For this network synchronization controller we use FPGA in Altera. FPGA includes 32bit CPU, DPRAM(dual port ram), digital input/output port, transmitter and receiver framer, phase difference detector. We also confirm that designed network synchronization controller satisfies the ITU-T G.813 timing requirements.

• The Journal of Korean Institute of Communications and Information Sciences
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• 제29권12B호
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• pp.1037-1041
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• 2004

In this paper we propose a new conceptual slave clock system in which remotely located clock is synchronized to the reference clock by intermediation of the satellite time, show a probability of adoption to real network by experiments. This new proposed method has lots of structural advantages over the existing methods because all of the node clocks can be maintained with the same hierarchical quality. The measurement results show that the accuracy of the experimental slave clock system can be kept within a few parts in 1012 and that the MTIE (Maximum Time Interval Error) meets the ITU-T Recommendation G.811 for the primary reference clock A prototype system having fully automatic operational functions has been realized, and it is expected to be commercially used as a node clock for synchronization in the digital communication network in the near future.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• 제12권4호
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• pp.644-650
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• 2001

A remotely located synchronization system which is locked to the remote master clock has been implemented by using GPS Common-View technique. The measurement results showed that the accuracy of the remote synchronization system could be kept within a few parts in $10^{-12}$ and MTIE(Maximum Time Interval Error) met the ITU-T Recommendation(G.811). A prototype system having fully automatic operational functions has been realized up to now and is expected to be used in the network synchronization in the near future.

• The Journal of Korean Institute of Communications and Information Sciences
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• 제34권11A호
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• pp.882-890
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• 2009

In this paper, we describe a compensation method that can be used for the situation where Loran receivers lose their phase lock to the received Loran signals when Loran signals are employed for the synchronization of national infrastructures such as telecommunication networks, electric power distribution and so on. In losing the phase lock to the received signals in a Loran receiver, the inner oscillator of the receiver starts free-running and the performance of the timing synchronization signals which are locked to the oscillator's phase is very severly degraded, so the timing accuracy under 1 us for a Primary Reference Clock (PRC) required in the International Telecommunications Union (ITU) G.811 standard can not be satisfied in the situation. Therefore, in this paper, we propose a method which can compensate the phase jump by using a compensation algorithm when a Loran receiver loses its phase lock and the performance evaluation of the proposed algorithm is achieved by the Maximum Time Interval Error (MTIE) of the measured data. From the performance evaluation results, it is observed that the requirement under 1 us for a PRC can be easily achieved by using the proposed algorithm showing about 0.6 us with under 30 minutes mean interval of smoothing with 1 hour period when the loss of phase lock occurs.

• The KIPS Transactions:PartC
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• 제12C권1호
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• pp.53-62
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• 2005

The NG-SDH system requires signal synchronization to synchronize incoming ethernet signal with GFP frame. The foreign nation research completes a chipset development until now and it secures a relation technique, but it does not secure a relation technique from domestic. Therefore, in this paper, we presented with signal synchronization method of Ethernet signal through GFP frame. We knew that the synchronized method of Ethernet signal through GFP-F must apply ingress & egress buffer and GFP Idle. We understood that the synchronized method of Ethernet signal through GFP-T must apply GFP Idle and $65B{\_}PAD$, and require maximum 3-bit addition & deletion of idle. Also we showed signal synchronization realization through simulation and obtained MTIE/TDEV characteristics and peak to peak jitter in egress output.

• The Journal of Korean Institute of Communications and Information Sciences
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• 제22권9호
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• pp.2062-2073
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• 1997

The important articles we must consider in SDH network and system design are the number of maximum nodes and clock characteristics of each node. In order to get these, the study of characteristics about some clock states, such as normal state and phase transient state, on the standard specifications is required. In this paper, we presented MTIE and TDEV characteristics with ITU-T & ANSI standard specifications in some clock states of the SDH linear networks, and proposed the number of maximum nodes satisfying above two standards. Also our resulsts are compared with AT&T's.

• Journal of The Institute of Information and Telecommunication Facilities Engineering
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• 제3권2호
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• pp.11-17
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• 2004

In this paper we propose a new conceptual system for a network clock in which all node clocks are simultaneously synchronized to the national standard by intermediation parameter of satellite time. Experiments have shown the possibility of its adoption by real networks. The new proposed method has various structural benefits, in particular all node clocks can be kept at the same hierarchical quality in contrast to the existing method. The measurement results show that the accuracy of the experimental slave clock system can be kept within a few parts In 1012 and the MTIE (Maximum Time Interval Error) sufficiently meets ITU-T G.811 for the primary reference clock. A prototype system with fully automatic operational functions has been realized at present and is expected to be directly used for communication network synchronization in the near future.

• The Journal of Korean Institute of Communications and Information Sciences
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• 제32권3A호
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• pp.237-246
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• 2007

Clock Synchronization is one of the most basic factors to be considered when we implement an indoor synchronization network for indoor positioning. In this paper, we present a new synchronization algorithm which does not employ time stamps in order to reduce the hardware complexity and data overhead. In addition to that, we describe an algorithm that is designed to compensate the frequency drift giving an serious impact on the synchronization performance. The performance evaluation of the proposed algorithm is achieved by investigating MTIE (Maximum Time Interval Error) values through simulations. In the simulations, the frequency drift values of the practical oscillators are used. From the simulation results, it is investigated that we can achieve the synchronization performance under 10 ns when we use 1 second synchronization interval with 1 ns resolution and TCXOs (Tmperature Compensated Cristal Oscillators) both in the master clock and the slave clock.