• Title/Summary/Keyword: MPEG-II

Search Result 49, Processing Time 0.026 seconds

Quality Assessment and Predistortion Evaluation of the Multi-channel Audio Codec according to the bitrate changing (압축율 변화에 따른 멀티채널 오디오의 품질 및 Predistortion 의 영향 평가)

  • Cha, Kyung-Hwan;Jang, Dae-Young;Kim, Sung-Han;Kim, Chun-Duck
    • The Journal of the Acoustical Society of Korea
    • /
    • v.15 no.2
    • /
    • pp.55-60
    • /
    • 1996
  • This paper describes the subjective assessment of the multi-channel audio quality according to the bitrate changing and evaluates the predistortion effect to avoid the unmasked noise after matrixing/dematrxing process in transmission and regeneration of the multi-channel audio. The simulation is processed by the perceptual coding that is MPEG-2 Audio layer II algorithm. We evaluate the quality improvement about predistortion using or not by 384, 320, 256, 128kbps. As the result of the double blind subjective assessment, 5 Grade-Impairment Scale is scored under minus one to 320kbps and so audio quality is evaluated to be perceptible, but not annoying in 3/2 channel. The effect of the predistortion is improved one level in 128kbps and especially speech test material I better improved than music test materials.

  • PDF

Hardware Implementation of Integer Transform and Quantization for H.264 (하드웨어 기반의 H.264 정수 변환 및 양자화 구현)

  • 임영훈;정용진
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.28 no.12C
    • /
    • pp.1182-1191
    • /
    • 2003
  • In this paper, we propose a new hardware architecture for integer transform, quantizer, inverse quantizer, and inverse integer transform of a new video coding standard H.264/JVT. We describe the algorithm and derive hardware architecture emphasizing the importance of area for low cost and low power consumption. The proposed architecture has been verified by PCI-interfaced emulation board using APEX-II Alters FPGA and also by ASIC synthesis using Samsung 0.18 um CMOS cell library. The ASIC synthesis result shows that the proposed hardware can operate at 100 MHz, processing more than 1,300 QCIF video frames per second. The hardware is going to be used as a core module when implementing a complete H.264 video encoder/decoder ASIC for real-time multimedia application.

GOP ARIMA based Bandwidth Prediction for Non-stationary VBR Traffic (MPEG VBR 트래픽을 위한 GOP ARIMA 기반 대역폭 예측기법)

  • Kang, Sung-Joo;Won, You-Jip
    • Proceedings of the KIEE Conference
    • /
    • 2004.11c
    • /
    • pp.301-303
    • /
    • 2004
  • In this work, we develop on-line traffic prediction algorithm for real-time VBR traffic. There are a number of important issues: (i) The traffic prediction algorithm should exploit the stochastic characteristics of the underlying traffic and (ii) it should quickly adapt to structural changes in underlying traffic. GOP ARIMA model effectively addresses this issues and it is used as basis in our bandwidth prediction. Our prediction model deploy Kalman filter to incorporate the prediction error for the next prediction round. We examine the performance of GOP ARIMA based prediction with linear prediction with LMS and double exponential smoothing. The proposed prediction algorithm exhibits superior performam againt the rest.

  • PDF

An Implementation of Monitoring system for using M-JPEC (M-JPEG을 이용한 모니터링 시스템 구현)

  • 안탁현;전광탁;박한엽;양해권;최연성
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
    • /
    • 1998.11a
    • /
    • pp.525-528
    • /
    • 1998
  • 본 논문은 현재 표준화 작업이 진행되고 있는 MS사의 M-JPEG을 이용하여 녹화 및 재생이 가능한 감시 시스템의 구현에 대해 설명한다. 기존 아날로그 감시 시스템의 단점인 여러번 재생시 화질 저하와 카메라에 비디오를 연결해야 하는 비효율성을 극복하기 위해 개발된 이 시스템은 사용자들에게 최대의 감시 효율을 제공할 수 있다. 이 무인 감시 시스템은 디지털 기술을 활용하여 모든 화상 처리와 화면 전환을 컴퓨터로 처리함으로서 여러 가지 다양한 모드의 감시환경을 제공하고 뛰어난 화면 capture기능으로 선명한 화질을 제공하여 감시 효과를 극대화시킬 수 있고 원하는 장면을 찾기 위한 검색 기능을 제공함으로서 사용자들에게 편리함을 제공할 수 있다. 본 시스템 구현에 사용된 H/W는 펜티엄-II 333과 카메라 16대 그리고 스위치 보드, MPEG capture 보드를 사용했으며 구동 S/W는 Visual C++로 제작하였다.

  • PDF

The Implementation of DSP-Based Real-Time Video Transmission System using In-Vehicle Multimedia Network (차량 내 멀티미디어 네트워크를 이용한 DSP 기반 실시간 영상 전송 시스템의 구현)

  • Jeon, Young-Joon;Kim, Jin-II
    • Journal of the Institute of Convergence Signal Processing
    • /
    • v.14 no.1
    • /
    • pp.62-69
    • /
    • 2013
  • This paper proposes real-time video transmission system by the car-mounted cameras based on MOST Network. Existing vehicles transmit videos by connecting the car-mounted cameras in the form of analog. However, the increase in the number of car-mounted cameras leads to development of the network to connect the cameras. In this paper, DSP is applied to process MPEG 2 encoding/decoding for real-time video transmission in a short period of time. MediaLB is employed to transfer data stream between DSP and MOST network controller. During this procedure, DSP cannot transport data stream directly from MediaLB. Therefore, FPGA is used to deliver data stream transmitting MediaLB to DSP. MediaLB is designed to streamline hardware/software application development for MOST Network and to support all MOST Network data transportation methods. As seen in this paper, the test results verify that real-time video transmission using proposed system operates in a normal matter.

The Implementation of Multi-Channel Audio Codec for Real-Time operation (실시간 처리를 위한 멀티채널 오디오 코덱의 구현)

  • Hong, Jin-Woo
    • The Journal of the Acoustical Society of Korea
    • /
    • v.14 no.2E
    • /
    • pp.91-97
    • /
    • 1995
  • This paper describes the implementation of a multi-channel audio codec for HETV. This codec has the features of the 3/2-stereo plus low frequency enhancement, downward compatibility with the smaller number of channels, backward compatibility with the existing 2/0-stereo system(MPEG-1 audio), and multilingual capability. The encoder of this codec consists of 6-channel analog audio input part with the sampling rate of 48 kHz, 4-channel digital audio input part and three TMS320C40 /DSPs. The encoder implements multi-channel audio compression using a human perceptual psychoacoustic model, and has the bit rate reduction to 384 kbit/s without impairment of subjective quality. The decoder consists of 6-channel analog audio output part, 4-channel digital audio output part, and two TMS320C40 DSPs for a decoding procedure. The decoder analyzes the bit stream received with bit rate of 384 kbit/s from the encoder and reproduces the multi-channel audio signals for analog and digital outputs. The multi-processing of this audio codec using multiple DSPs is ensured by high speed transfer of date between DSPs through coordinating communication port activities with DMA coprocessors. Finally, some technical considerations are suggested to realize the problem of real-time operation, which are found out through the implementation of this codec using the MPEG-2 layer II sudio coding algorithm and the use of the hardware architecture with commercial multiple DSPs.

  • PDF

The Design of a Multiplexer for Multiview Image Processing

  • Kim, Do-Kyun;Lee, Yong-Joo;Koo, Gun-Seo;Lee, Yong-Surk
    • Proceedings of the IEEK Conference
    • /
    • 2002.07a
    • /
    • pp.682-685
    • /
    • 2002
  • In this paper, we defined necessary operations and functional blocks of a multiplexer for 3-D video systems and present our multiplexer design. We adopted the ITU-T's recommendation(H.222.0) to define the operations and functions of the multiplexer and explained the data structures and details of the design for multiview image processing. The data structure of TS(Transport Stream) and PES (Packetized Elementary Stream) in ITU-T Recommendation H.222.0 does not fit our multiview image processing system, because this recommendation is fur wide scope of transmission of non-telephone signals. Therefore, we modified these TS and PES stream structures. The TS is modified to DSS(3D System Stream) and PES is modified to SPDU(DSS Program Data Unit). We constructed the multiplexer through these modified DSS and SPDU. The number of multiview image channels is nine, and the image class employed is MPEG-2 SD(Standard Definition) level which requires a bandwidth of 2∼6 Mbps. The required clock speed should be faster than 54(= 6 ${\times}$ 9)㎒ which is the outer interface clock speed. The inside part of the multiplexer requires a clock speed of only 1/8 of 54㎒, since the inside part of the multiplexer operates by the unit of byte. we used ALTERA Quartus II and the FPGA verification for the simulation.

  • PDF

A Study on the Individual Recognition with Skull Image Composition (두개골 영상합성에 의한 개인감정시스템 연구-II)

  • 송현교;이양원;강민구
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.2 no.1
    • /
    • pp.3-10
    • /
    • 1998
  • In this paper, a new superimposition scheme using a computer vision system was proposed with 7 pairs of skull and ante-mortem photographs, which were already identified through other tests and DNA fingerprints at the Korea National Institute of Scientific Investigation. At this computer vision system, an unidentified skull was caught by video-camcoder with the MPEG and a ante-mortem photograph was scanned by scanner. These two images were processed and superimposed using pixel processing. Recognition of the individual identification by anatomical references was performed on the two superimposed images. This image processing techniques for the superimposition of skull and ante-morterm photographs simplify used the previous approach taking skull photographs and developing it to the same size as the ante-mortem Photographs. This system using various image Processing techniques on computer screen, a more precise and time-saving superimposition technique could be able to be applied in the area of computer individual identification.

  • PDF

A Study on Motion Estimator Design Using DCT DC Value (DCT 직류 값을 이용한 움직임 추정기 설계에 관한 연구)

  • Lee, Gwon-Cheol;Park, Jong-Jin;Jo, Won-Gyeong
    • Journal of the Institute of Electronics Engineers of Korea SP
    • /
    • v.38 no.3
    • /
    • pp.258-268
    • /
    • 2001
  • The compression method is necessarily used to send the high quality moving picture that contains a number of data in image processing. In the field of moving picture compression method, the motion estimation algorithm is used to reduce the temporal redundancy. Block matching algorithm to be usually used is distinguished partial search algorithm with full search algorithm. Full search algorithm be used in this paper is the method to compare the reference block with entire block in the search window. It is very efficient and has simple data flow and control circuit. But the bigger the search window, the larger hardware size, because large computational operation is needed. In this paper, we design the full search block matching motion estimator. Using the DCT DC values, we decide luminance. And we apply 3 bit compare-selector using bit plane to I(Intra coded) picture, not using 8 bit luminance signals. Also it is suggested that use the same selective bit for the P(Predicted coded) and B(Bidirectional coded) picture. We compare based full search method with PSNR(Peak Signal to Noise Ratio) for C language modeling. Its condition is the reference block 8$\times$8, the search window 24$\times$24 and 352$\times$288 gray scale standard video images. The result has small difference that we cannot see. And we design the suggested motion estimator that hardware size is proved to reduce 38.3% for structure I and 30.7% for structure II. The memory is proved to reduce 31.3% for structure I and II.

  • PDF