• Title/Summary/Keyword: MPEG-1 Decoder

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Synchronization of audio and video streams on multi-threading MPEG-1 decoder using shared buffers (다중 쓰래딩 기법의 MPEG-1 디코더에서 공유버퍼를 이용한 오디오/비디오 스트림의 동기화)

  • 박태강;이호석
    • Proceedings of the Korean Information Science Society Conference
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    • 1999.10b
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    • pp.221-223
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    • 1999
  • 소프트웨어로 MPEG-1 디코더의 구현이 가능하다. 소프트웨어 MPEG-1 디코더의 문제 중 하나는 MPEG-1 압축 알고리즘의 특징상 각각의 영상들이 서로 다른 압축율로 압축되기 때문에 재생시에 디코더에 걸리는 부하가 매우 불규칙적이라는 점이다. 이 문제는 MPEG-1 디코더를 보다 작은 실행 단위인 쓰래드로 나누어 처리함으로써 효율적으로 해결할 수 있다. 이때 독립적인 실행 흐름을 가지는 쓰래드들간의 데이터 전달을 위하여 공유버퍼를 사용하게 된다. 본 논문에서는 다중 쓰래드로 구성된 소프트웨어 MPEG-1 디코더에서 쓰래드들 간의 데이터 전달에 사용되는 공유 버퍼를 이용하여 오디오와 비디오 스트림의 동기화를 효과적으로 수행하는 기법을 소개한다.

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Design Optimization of MPEG-2 AAC Decoder (MPEG-2 AAC 복호화 시스템의 구조 제안 및 구현)

  • 방경호;김준석;윤대희
    • Proceedings of the IEEK Conference
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    • 2001.09a
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    • pp.257-260
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    • 2001
  • 본 논문에서는 2 채널 MAIN 프로필 MPEG-2 AAC 복호화 시스템의 구조를 제안하고 구현하였다. 복호화 알고리듬의 구조적인 모듈화에 근거하여, 시스템 설계 과정에서 전체 시스템을 3 개의 하드웨어 모듈로 분할하였다. 전체 시스템은 허프만 복호화기, 예측기, 20 비트 고정소수점 DSP 코어로 이루어져 있다. 허프만 복호화기는 주어진 작업을 1 클럭 사이클 내에 수행할 수 있는 고속의 하드와이어드 모듈이고, 예측기는 높은 해상도를 가지고 다른 모듈들과 병렬처리가 가능한 구조를 가진 모듈이다. 구현된 시스템은 16.9 MIPS 로 2 채널의 MPEG-2 AAC 비트열을 고음질로 복호화할 수 있다.

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VLSI Design of MPEG-2 AAC Audio Decoder (MPEG-2 AAC 오디오 복호화기의 VLSI 설계)

  • 방경호;김준석;정남훈;이근섭;박영철;윤대희
    • Proceedings of the IEEK Conference
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    • 2000.09a
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    • pp.247-250
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    • 2000
  • 본 논문에서는 MPEG-2 AAC 오디오 복호화 시스템을 효율적으로 설계하고 구현하였다. 구현된 시스템은 2채널의 메인 프로필 MPEG-2 AAC 비트열을 실시간으로 복호화하고, 32, 44.1, 48kHz의 표본화 주파수를 지원하여, 표준안에서 제안하는 툴 중 커플링 채널을 제외한 모든 툴을 지원한다. 설계된 시스템은 허프만 복호화와 예측 과정을 수행하는 두개의 독립된 모듈과 Programmable DSP 코어의 혼합 구조(hybrid architecture)로 최적화된 구조를 갖는다.

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VLSI Design of MPEG-2 AAC Decoder (VLSI를 이용한 MPEG-2 AAC 복호화기 설계)

  • 이근섭;정남훈;방경호;윤대희
    • Proceedings of the IEEK Conference
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    • 1999.06a
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    • pp.1099-1102
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    • 1999
  • This paper presents a real-time MPEG-2 AAC decoding system, which can decode 2-channel main profile MPEG-2 AAC bitstream. The proposed system supports all decoding tools except for coupling channel tool, and provides sampling rates of 32, 44.1, 48 KHz. The system consists of a simple programmable DSP core and two hardwired logic modules that perform Huffman decoding and prediction for real-time implementation.

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Design of Decoder for H.264/AVC Intra Prediction Mode (H.264/AVC 인트라 예측모드용 디코더 설계)

  • Jung, Duck-Young;Sonh, Seung-Il
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • v.9 no.1
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    • pp.1046-1050
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    • 2005
  • 영상 정보의 발전으로 다양한 멀티미디어 서비스를 가능하게 하였고 네트워크와 IT의 발전으로 사용자가 풍부한 정보를 접할 수 있는 기회를 제공하였다. 이러한 동영상과 정지영상의 많은 정보를 압축하는 여러 방식 중에서 디지털 비디오 압축 관련 국제 표준안 중 MPEG-4와 H.264가 발표되었다. 유연성이 좋은 MPEG-4와 달리 H.264는 비디오 프레임의 효율적인 압축과 신뢰성을 강조 한다. 특히 H.264의 압축 기술은 HDTV처럼 큰 영상 뿐 아니라 카메라폰이나 DMB등의 특히 작은 크기의 영상에서 고품질의 영상을 보다 효율적으로 제공 한다. 본 논문은 기존의 동영상 압축 표준에 비하여 높은 압축성능과 유연성의 장점을 가지고 있고 표준 H.264/AVC에서 공간적 예측을 사용하여 비디오 프레임을 압축하는 방법인 Intra coding 에서 사용하는 여러 모드 중 4*4 예측모드를 연구하여 C언어를 이용한 최적화된 시뮬레이션과 Intra coding decoder의 성능평가를 통한 최적화를 실시하였고, 최적화된 예측 정보를 바탕으로 Intra coding decoder를 VHDL언어를 이용하여 하드웨어로 구현하였다.

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Real-Time Implementation of MPEG-1 Layer III Audio Decoder Using TMS320C6201 (TMS320C6201을 이용한 MPEG-1 Layer III 오디오 디코더의 실시간 구현)

  • 권홍석;김시호;배건성
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.25 no.8B
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    • pp.1460-1468
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    • 2000
  • The goal of this research is the real-time implementation of MPEG-1 Layer III audio decoder using the fixed-point digital signal processor of TMS320C6201 The main job for this work is twofold: one is to convert floating-point operation in the decoder into fixed-point operation while maintaining the high resolution, and the other is to optimize the program to make it run in real-time with memory size as small as possible. We, especially, devote much time to the descaling module in the decoder for conversion of floating-point operation into fixed-point operation with high accuracy. The inverse modified cosine transform(IMDCT) and synthesis polyphase filter bank modules are optimized in order to reduce the amount of computation and memory size. After the optimization process, in this paper, the implemented decoder uses about 26% of maximum computation capacity of TMS320C6201. The program memory, data ROM, data RAM used in the decoder are about 6.77kwords, 3.13 kwords and 9.94 kwords, respectively. Comparing the PCM output of fixed-point computation with that of floating-point computation, we achieve the signal-to-noise ratio of more than 60 dB. A real-time operation is demonstrated on the PC using the sound I/O and host communication functions in the EVM board.

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Hardware Channel Decoder for Holographic WORM Storage (홀로그래픽 WORM의 하드웨어 채널 디코더)

  • Hwang, Eui-Seok;Yoon, Pil-Sang;Kim, Hak-Sun;Park, Joo-Youn
    • Transactions of the Society of Information Storage Systems
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    • v.1 no.2
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    • pp.155-160
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    • 2005
  • In this paper, the channel decoder promising reliable data retrieving in noisy holographic channel has been developed for holographic WORM(write once read many) system. It covers various DSP(digital signal processing) blocks, such as align mark detector, adaptive channel equalizer, modulation decoder and ECC(error correction code) decoder. The specific schemes of DSP are designed to reduce the effect of noises in holographic WORM(H-WORM) system, particularly in prototype of DAEWOO electronics(DEPROTO). For real time data retrieving, the channel decoder is redesigned for FPGA(field programmable gate array) based hardware, where DSP blocks calculate in parallel sense with memory buffers between blocks and controllers for driving peripherals of FPGA. As an input source of the experiments, MPEG2 TS(transport stream) data was used and recorded to DEPROTO system. During retrieving, the CCD(charge coupled device), capturing device of DEPROTO, detects retrieved images and transmits signals of them to the FPGA of hardware channel decoder. Finally, the output data stream of the channel decoder was transferred to the MPEG decoding board for monitoring video signals. The experimental results showed the error corrected BER(bit error rate) of less than $10^{-9}$, from the raw BER of DEPROTO, about $10^{-3}$. With the developed hardware channel decoder, the real-time video demonstration was possible during the experiments. The operating clock of the FPGA was 60 MHz, of which speed was capable of decoding up to 120 mega channel bits per sec.

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Design on MPEC2 AAC Decoder

  • NOH, Jin Soo;Kang, Dongshik;RHEE, Kang Hyeon
    • Proceedings of the IEEK Conference
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    • 2002.07c
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    • pp.1567-1570
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    • 2002
  • This paper deals with FPGA(Field Programmable Gate Array) implementation of the AAC(Advanced Audio Coding) decoder. On modern computer culture, according to the high quality data is required in multimedia systems area such as CD, DAT(Digital Audio Tape) and modem. So, the technology of data compression far data transmission is necessity now. MPEG(Moving Picture Experts Group) would be a standard of those technology. MPEG-2 AAC is the availableness and ITU-R advanced coding scheme far high quality audio coding. This MPEG-2 AAC audio standard allows ITU-R 'indistinguishable' quality according to at data rates of 320 Kbit/sec for five full-bandwidth channel audio signals. The compression ratio is around a factor of 1.4 better compared to MPEG Layer-III, it gets the same quality at 70% of the titrate. In this paper, for a real time processing MPEG2 AAC decoding, it is implemented on FPGA chip. The architecture designed is composed of general DSP(Digital Signal Processor). And the Processor designed is coded using VHDL language. The verification is operated with the simulator of C language programmed and ECAD tool.

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Multi-symbol Accessing Huffman Decoding Method for MPEG-2 AAC

  • Lee, Eun-Seo;Lee, Kyoung-Cheol;Son, Kyou-Jung;Moon, Seong-Pil;Chang, Tae-Gyu
    • Journal of Electrical Engineering and Technology
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    • v.9 no.4
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    • pp.1411-1417
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    • 2014
  • An MPEG-2 AAC Huffman decoding method based on the fixed length compacted codeword tables, where each codeword can contain multiple number of Huffman codes, was proposed. The proposed method enhances the searching efficiency by finding multiple symbols in a single search, i.e., a direct memory reading of the compacted codeword table. The memory usage is significantly saved by separately handling the Huffman codes that exceed the length of the compacted codewords. The trade-off relation between the computational complexity and the amount of memory usage was analytically derived to find the proper codeword length of the compacted codewords for the design of MPEG-2 AAC decoder. To validate the proposed algorithm, its performance was experimentally evaluated with an implemented MPEG-2 AAC decoder. The results showed that the computational complexity of the proposed method is reduced to 54% of that of the most up-to-date method.

Kalman filter based Motion Vector Recovery for H.264 (H.264 비디오 표준에서의 칼만 필터 기반의 움직임벡터 복원)

  • Ko, Ki-Hong;Kim, Seong-Whan
    • The KIPS Transactions:PartD
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    • v.14D no.7
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    • pp.801-808
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    • 2007
  • Video coding standards such as MPEG-2, MPEG-4, H.263, and H.264 transmit a compressed video data using wired/wireless communication line with limited bandwidth. Because highly compressed bit-streams is likely to fragile to error from channel noise, video is damaged by error. There have been many research works on error concealment techniques, which recover transmission errors at decoder side [1, 2]. We designed an error concealment technique for lost motion vectors of H.264 video coding. In this paper, we propose a Kalman filter based motion vector recovery scheme, and experimented with standard video sequences. The experimental results show that our scheme restores original motion vector with more precision of 0.91 - 1.12 on average over conventional H.264 decoding with no error recovery.