• Proceedings of the KIPE Conference
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• 1997.07a
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• pp.131-134
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• 1997

McT는 MOS-게이트형 사이리스터로써 MOS-게이트형 턴-온 및 턴-오프 특성과 낮은 도통 전압을 나타내는 소자이다. 그러나 SOA(Safe Operation Area)가 상대적으로 작기 때문에 스너버 회로를 필요로 한다. 본 논문에서는 간단한 MCT PSPICE 모델을 사용하여 스위칭 특성과 RCD 스너버의 특성을 분석하였고 스너버 회로 설계방식을 제안하였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.9
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• pp.547-550
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• 2014

In this study, the electrical characteristics of the nickel (Ni)/carbon nanotube (CNT)/$SiO_2$ structures were investigated in order to analyze the mechanism of CNT in MOS device structures. We fabricated 4H-SiC MOS capacitors with or without CNTs. CNT was dispersed by isopropyl alcohol. The capacitance-voltage (C-V) and current-voltage (I-V) are characterized. Both devices were measured by Keithley 4200 SCS. The experimental flatband voltage ($V_{FB}$) shift was positive. Near-interface trap charge density ($N_{it}$) and negative oxide trap charge density ($N_{ox}$) value of CNT embedded MOS capacitors was less than that values of reference samples. Also, the leakage current of CNT embedded MOS capacitors is higher than reference samples. It has been found that its oxide quality is related to charge carriers and/or defect states in the interface of MOS capacitors.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.12
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• pp.6046-6051
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• 2012

In this paper, we designed a Chua's chaotic circuit using transcondcutor based nonlinear resistor for secure communication applications. Proposed chaotic circuit consist of passive devices such as L and C, a MOS based variable resistor and a transcondcutor based Chua's diode. From SPICE simulation results, the proposed circuit showed variable chaotic dynamics through time waveforms, frequency analysis and phase plots.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.130-131
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• 2005

In the era of submicron devices, super ultra thin gate oxide characteristics are required. Titanium silicide process has studied gate oxide reliability and dielectric strength characteristics as the composition of gate electrode. In this study the author observed process characteristics on MOS structure. In view point of the process characteristics of MOS capacitor, the oxygen & Ti, Si2 was analyzed by SIMS analysis on before and after annealing with 1,2 step silicidation, the Ti contents[Count/sec]of $9.5{\times}1018$ & $6.5{\times}1018$ on before and after 2'nd anneal. The oxygen contents[Count/sec] of $4.3{\times}104$ & $3.65{\times}104$, the Si contents[Count/sec] of $4.2{\times}104$ & $3.7{\times}104$ on before and after 2'nd anneal. The rms value[A] was 4.98, & 4.03 on before and after 2'nd anneal.

• Proceedings of the KIEE Conference
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• 1994.07a
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• pp.237-239
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• 1994

The MOS-controlled thyristor(MCT) is a new power semi-conductor device that combines four layers thyristor structure presenting regenerative action and MOS-gate providing controlled turn-on and turn-off. The MCT has very fast switching speed owing to voltage controlled MOS-gate, and very low on-state voltage drop resulting from regenerative action of four layers thyristor structure. In addition, because of a higher dv/dt rating and di/dt rating, gate drive circuit and snubber circuit can be simpler comparing to other power switching devices. So recently much interest and endeavor is being applied to develop the performance and ratings of the MCT. This paper describes the switching characteristic of the MCT for its practical applications and presents a model for PSPICE circuit simulation. The model for PSPICE circuit simulation is compared to the experimental result using MCTV75P60F1 made by Harris co..

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.6
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• pp.107-116
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• 1994

In this paper, The electrical properties of MOS capacitors and transistoras with gate of in-situ doped amorphous Si and poly Si doped by POCI$_3$. Under constant current F-N stress, MOS capacitors with in-situ doped amorphous Si gate have shown the best resistance to degradation in reliabilty properties such as increase of leakage current, shift of gate voltage (V$_{g}$). shift of flat band voltage (V$_{fb}$) and charge to breakdown(Q$_{bd}$). Also, MOSFETs with in-situ doped amorphous Si gate have shown to have less degradation in transistor properties such as threshold voltage, transconductance and drain current. These improvements observed in MOS devices with in-situ doped amorphous Si gate is attributed to less local thinning spots at the gate/SiO$_2$ interface, caused by the large grain size and the smoothness of the surface at the gate/SiO$_2$ interface.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.21-27
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• 2009

In this work, Er-silicided SB-SOI nMOSFET and Pt-silicided SB-SOI pMOSFET have been fabricated to investigate the current-voltage characteristics of Schottky barrier SOI nMOS and pMOS at elevated temperature. The dominant current transport mechanism of SB nMOS and pMOS is discussed using the measurement results of the temperature dependence of drain current with gate voltages. It is observed that the drain current increases with the increase of operating temperature at low gate voltage due to the increase of thermal emission and tunneling current. But the drain current is decreased at high gate voltage due to the decrease of the drift current. It is observed that the ON/Off current ratio is decreased due to the increased tunneling current from the drain to channel region although the ON current is increased at elevated temperature. The threshold voltage variation with temperature is smaller and the subthreshold swing is larger in SB-SOI nMOS and pMOS than in SOI devices or in bulk MOSFETs.

• Journal of Korea Society of Industrial Information Systems
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• v.7 no.5
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• pp.147-153
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• 2002

In this paper, a substrate network model to be used with BSIM3 MOSFET model for submicron MOSFETs in giga hertz frequencies and its direct parameter extraction with physically meaningful values are proposed. The proposed substrate network model includes a conventional resistance and single inductance originated from ring-type substrate contacts around active devices. Model parameters are extracted from S-parameter data measured from common-bulk configured MOS transistors with floating gate and use where needed without any optimization process. The proposed modeling technique has been applied to various-sized MOS transistors. The substrate model has been validated for frequency up to 300Hz.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.6
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• pp.2697-2701
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• 2012

The yield of OTP devices using anti-fuse MOS capacitor have been affected by the input resistance, the size of the pass transistor and the read transistor, and the readout voltage of programed cell. To investigate the element which gives an effect to yield, we analyze the full map data of the resistance characterization of OTP device and those data in a various experimental condition. As a result, we got the optimum conditions which is necessary to the yield improvement. The optimum conditions are as follows: Input resistance is 50 ohms, the channel length of pass transistor is 10um, read voltage is 2.8 volt, respectively.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.577-580
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• 1998

This paper presents the characteristics of each MOS device and Bipolar device, then investigates about how these devices take effect on BiCMOS inverter from 300K to 470K. The turn-off and Logic swing characteristics of BiCMOS inverter are degraded by the electrical characteristics of the MOS to around 400K, but over that temperature enhanced by the characteristics of the Bipolar transistor.