• Title/Summary/Keyword: MOM capacitor

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A Study on the Design and Characteristics of thin-film L-C Band Pass Filter

  • Kim In-Sung;Song Jae-Sung;Min Bok-Ki;Lee Won-Jae;Muller Alexandru
    • KIEE International Transactions on Electrophysics and Applications
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    • v.5C no.4
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    • pp.176-179
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    • 2005
  • The increasing demand for high density packaging technologies and the evolution to mixed digital and analogue devices has been the con-set of increasing research in thin film multi-layer technologies such as the passive components integration technology. In this paper, Cu and TaO thin film with RF sputtering was deposited for spiral inductor and MOM capacitor on the $SiO_2$/Si(100) substrate. MOM capacitor and spiral inductor were fabricated for L-C band pass filter by sputtering and lift-off. We are analyzed and designed thin films L-C passive components for band pass filter at 900 MHz and 1.8 GHz, important devices for mobile communication system. Based on the high-Q values of passive components, MOM capacitor and spiral inductors for L-C band pass filter, a low insertion loss of L-C passive components can be realized with a minimized chip area. The insertion loss was 3 dB for a 1.8 GHz filter, and 5 dB for a 900 MHz filter. This paper also discusses a analysis and practical design to thin-film L-C band pass filter.

A 10-bit 10-MS/s Asynchronous SAR analog-to-digital converter with digital-to-analog converter using MOM capacitor (MOM 커패시터를 사용한 디지털-아날로그 변환기를 가진 10-bit 10-MS/s 비동기 축차근사형 아날로그-디지털 변환기)

  • Jeong, Yeon-Ho;Jang, Young-Chan
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.18 no.1
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    • pp.129-134
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    • 2014
  • This paper presents a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) which consists of a digital-to-analog converter (DAC), a SAR logic, and a comparator. The designed asynchronous SAR ADC with a rail-to-rail input range uses a binary weighted DAC using metal-oxide-metal (MOM) capacitor to improve sampling rate. The proposed 10-bit 10-MS/s asynchronous SAR ADC is fabricated using a 0.18-${\mu}m$ CMOS process and its active area is $0.103mm^2$. The power consumption is 0.37 mW when the voltage of supply is 1.1 V. The measured SNDR are 54.19 dB and 51.59 dB at the analog input frequency of 101.12 kHz and 5.12 MHz, respectively.