• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.4
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• pp.240-245
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• 2006

Viterbi decoder is composed of BMU(Branch metric Unit), ACSU(Add Compare Select Unit), and SMU(Survivor path Memory Unit). For high speed viterbi decoders, ACSU is the main bottleneck due to the compare-select and feedback operation. Thus, many studies have been advanced to solve the problem. For example, M-step look ahead technique and Minimized method are typical high speed algorithms. In this paper, we designed a bit-level ACSU(K=3, R=1/2, 4bit soft decision) based on those algorithms and switched the matrix product order in the backward direction of Minimized method so as to apply Code-Optimized-Array in order to reduce the area complexity. For experimentation, we synthesized our design by using SYNOPSYS Design compiler, with TSMC 0.18 um library, and verified the timing by using CADENCE verilog-XL.

• Proceedings of the Korea Inteligent Information System Society Conference
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• 2006.06a
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• pp.311-315
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• 2006

Viterbi decoder는 크게 BM(Branch metric), ACS(Add-Compare-Select), SM(Survivor Memory) block 으로 구성되어 있다. 이중 ACSU 부분은 고속 데이터 처리를 위한 bottleneck이 되어 왔으며, 이의 해결을 위한 많은 연구가 활발히 진행되어 왔다. look ahead technique은 ACSU를 M-step으로 처리하고 CS(Carry save) number를 사용한 새로운 비교 알고리즘을 제안하여 high throughput을 추구했으며, minimized method는 block processing 방식으로 forward, backward 방향으로 decoding을 수행하여 ACSU 부분의 feedback을 완전히 제거하여 exteremely high throughput 을 추구하고 있다. 이에 대해 look ahead technique 의 기본 PE(Processing Element)를 바탕으로 minimized method 알고 리즘의 core block 을 bit-level 로 구현하였으며 : code converter 를 이용하여 CS number 가운데 redundat number(l)를 제거하여 비교기를 더 간단히 하였다. SYNOPSYS의 Design compiler 와 TSMC 0.18 um library 를 이용하여 합성하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.125-136
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• 2009

This paper presents a high-speed low-complexity two-bit level pipelined Viterbi decoder architecture for MB-OFDM UWB systems. As the add-compare-select unit (ACSU) is the main bottleneck of the Viterbi decoder, this paper proposes a novel two-bit level pipelined MSB-first ACSU, which is based on 2-step look-ahead techniques to reduce the critical path. The proposed ACSU architecture requires approximately 12% fewer gate counts and 9% faster speed than the conventional MSB-first ACSU. The proposed Viterbi decoder was implemented with $0.18-{\mu}m$ CMOS standard cell technology and a supply voltage of 1.8V. It operates at a clock frequency of 870 MHZ and has a throughput of 1.74 Gb/s.

• The Journal of Korea Robotics Society
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• v.17 no.2
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• pp.142-151
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• 2022

With the advent of the 4th industrial revolution, autonomous driving technology is being commercialized in various industries. However, research on autonomous driving so far has focused on platforms with wheel-type platform. Research on a tracked platform is at a relatively inadequate step. Since the tracked platform has a different driving and steering method from the wheel-type platform, the existing research cannot be applied as it is. Therefore, a path-tracking algorithm suitable for a tracked platform is required. In this paper, we studied a path-tracking algorithm for a tracked platform based on a GPS sensor. The existing Pure Pursuit algorithm was applied in consideration of the characteristics of the tracked platform. And to compensate for "Cutting Corner", which is a disadvantage of the existing Pure Pursuit algorithm, an algorithm that changes the LAD according to the curvature of the path was developed. In the existing pure pursuit algorithm that used a tracked platform to drive a path including a right-angle turn, the RMS path error in the straight section was 0.1034 m and the RMS error in the turning section was measured to be 0.2787 m. On the other hand, in the variable LAD algorithm, the RMS path error in the straight section was 0.0987 m, and the RMS path error in the turning section was measured to be 0.1396 m. In the turning section, the RMS path error was reduced by 48.8971%. The validity of the algorithm was verified by measuring the path error by tracking the path using a tracked robot platform.