• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제44회 동계 정기학술대회 초록집
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• pp.313-313
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• 2013

For high-performance TFT (Thin film transistor), poly-crystalline semiconductor thin film with low resistivity and high hall carrier mobility is necessary. But, conventional SPC (Solid phase crystallization) process has disadvantages in fabrication such as long annealing time in high temperature or using very expensive Excimer laser. On the contrary, MIC (Metal-induced crystallization) process enables semiconductor thin film crystallization at lower temperature in short annealing time. But, it has been known that the poly-crystalline semiconductor thin film fabricated by MIC methods, has low hall mobility due to the residual metals after crystallization process. In this study, Ni metal was shallow implanted using PIII&D (Plasma Immersion Ion Implantation & Deposition) technique instead of depositing Ni layer to reduce the Ni contamination after annealing. In addition, the effect of external magnetic field during annealing was studied to enhance the amorphous silicon thin film crystallization process. Various thin film analytical techniques such as XRD (X-Ray Diffraction), Raman spectroscopy, and XPS (X-ray Photoelectron Spectroscopy), Hall mobility measurement system were used to investigate the structure and composition of silicon thin film samples.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.444-445
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• 2009

The metallic contact system of silicon solar cell must have several properties, such as low contact resistance, easy application and good adhesion. Ni is shown to be a suitable barrier to Cu diffusion as well as desirable contact metal to silicon. Nickel monosilicide(NiSi) has been suggested as a suitable silicide due to its lower resistivity, lower sintering temperature and lower layer stress than $TiSi_2$. Copper and Silver can be plated by electro & light-induced plating method. Light-induced plating makes use the photovoltaic effect of solar cell to deposit the metal on the front contact. The cell is immersed into the electrolytic plating bath and irradiated at the front side by light source, which leads to a current density in the front side grid. Electroless plated Ni/ Electro&light-induced plated Cu/ Light-induced plated Ag contact solar cells result in an energy conversion efficiency of 16.446 % on $0.2\sim0.6\;{\Omega}{\cdot}cm$, $20\;\times\;20\;mm^2$, CZ(Czochralski) wafer.

• 한국전기전자재료학회논문지
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• 제24권2호
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• pp.121-125
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• 2011

Ribbon silicon solar cells have been investigated because they can be produced with a lower material cost. However, it is very difficult to get good texturing with a conventional acid solution. To achieve high efficiency should be minimized for the reflectance properties. In this paper, acid vapor texturing and anti-reflection coating of $SiN_x$ was applied for EFG Ribbon Si Wafer. P-type ribbon silicon wafer had a thickness of 200 ${\mu}m$ and a resistivity of 3 $\Omega-cm$. Ribbon silicon wafers were exposed in an acid vapor. Acid vapor texturing was made by reaction between the silicon and the mixed solution of HF : $HNO_3$. After acid vapor texturing process, nanostructure of less than size of 1 ${\mu}m$ was formed and surface reflectance of 6.44% was achieved. Reflectance was decreased to 2.37% with anti-reflection coating of $SiN_x$.

• Journal of Information Display
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• 제11권1호
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• pp.12-16
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• 2010

The effect of the crystallization and activated annealing of Si films using an excimer laser and the new CW blue laser are described and compared with furnace annealing for application in advanced TFTs and for future applications. Pulsed excimer laser annealing (ELA) is currently being used extensively as a low-temperature poly-silicon (LTPS) process on glass substrates as its efficiency is high in the ultra-violet (UV) region for thin Si films with thickness of 40-60 nm. ELA enables extremely low resistivity relating to high crystallinity for both the n- and p-type Si films. On the other hand, CW blue laser diode annealing (BLDA) enables the smooth Si surface to have arbitral crystal grains from micro-grains to an anisotropic huge grain structure only by controlling its power density. Both annealing techniques are expected to be applied in the future advanced TFT systems.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.1415-1417
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• 2009

High transmittance and low resistance index matched transparent conducting oxide (IMTCO) coated glass was prepared and characterized. IMTCO was deposited by RF magnetron sputtering with the thickness of 15nm and 90nm thick anti-reflection layer was evaporated. To modify surface to hydrophilic, in-situ plasma treatment was also performed. IMTCO coated glass exhibited 96.6% of transmittance in the wavelength range of 400~700nm which is relatively high value compared to commercially available IMTCO glass. The sheet resistance uniformity was measured to be 1.53%.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2018년도 춘계학술대회 논문집
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• pp.140-140
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• 2018

The 3D interconnect technologies have been appeared, as the density of Integrated Circuit (IC) devices increases. Through Silicon Via (TSV) process is an important technology in the 3D interconnect technologies. And the process is used to form a vertically electrical connection through silicon dies. This TSV process has some advantages that short length of interconnection, high interconnection density, low electrical resistance, and low power consumption. Because of these advantages, TSVs could improve the device performance higher. The fabrication process of TSV has several steps such as TSV etching, insulator deposition, seed layer deposition, metallization, planarization, and assembly. Among them, TSV metallization (i.e. TSV filling) was core process in the fabrication process of TSV because TSV metallization determines the performance and reliability of the TSV interconnect. TSVs were commonly filled with metals by using the simple electrochemical deposition method. However, since the aspect ratio of TSVs was become a higher, it was easy to occur voids and copper filling of TSVs became more difficult. Using some additives like an accelerator, suppressor and leveler for the void-free filling of TSVs, deposition rate of bottom could be fast whereas deposition of side walls could be inhibited. The suppressor was adsorbed surface of via easily because of its higher molecular weight than the accelerator. However, for high aspect ratio TSV fillers, the growth of the top of via can be accelerated because the suppressor is replaced by an accelerator. The substitution of the accelerator and the suppressor caused the side wall growth and defect generation. The suppressor was used as Single additive electrodeposition of TSV to overcome the constraints. At the electrochemical deposition of high aspect ratio of TSVs, the suppressor as single additive could effectively suppress the growth of the top surface and the void-free bottom-up filling became possible. Generally, copper was used to fill TSVs since its low resistivity could reduce the RC delay of the interconnection. However, because of the large Coefficients of Thermal Expansion (CTE) mismatch between silicon and copper, stress was induced to the silicon around the TSVs at the annealing process. The Keep Out Zone (KOZ), the stressed area in the silicon, could affect carrier mobility and could cause degradation of the device performance. Cobalt can be used as an alternative material because the CTE of cobalt was lower than that of copper. Therefore, using cobalt could reduce KOZ and improve device performance. In this study, high-aspect ratio TSVs were filled with cobalt using the electrochemical deposition. And the filling performance was enhanced by using the suppressor as single additive. Electrochemical analysis explains the effect of suppressor in the cobalt filling bath and the effect of filling behavior at condition such as current type was investigated.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1993년도 춘계학술대회 논문집
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• pp.96-99
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• 1993

대면적 액정 표시판 (Liquid Crystal Display:LCD) panel내(內)의 구동소자인 비정질 실리콘 (amorphous silicon) 박막 트랜지스터 (Thin Film Transistor:TFT)의 구동신호전달 소자특성 향상을 위한 본(本) 연구의 목적은 액정 panel TFT 제조공정 상(上)의 증착금속 전극박막들의 Test Elements Group(TEG) metal line pattern별(別) 전기적 저항특성 평가에 있다. 현(現) TFT 전극용(用)으로 개발이 진행 중(中)인 Aluminum(Al), Tantalum(Ta) 및 Chromium(Cr) 이 특성평가 대상 금속 박막으로 선정 되었으며, 이들 금속막의 증착 thickness 와 TEG metal line width가 저항특성 변수로 성립 되었다. 본(本) 실험을 통해 금속 박막의 TEG line width별(別) 체적(體積)저항 (bulk resistance), 면(面)저항(sheet resistance), 비(比)저항 (resistivity) 및 기판 상(上)의 metal pattern 위치 변화에 따른 전기적 저항 uniformity 특성변화 평가가 있었다. TEG metal line 측정 변위에 따른 저항율의 선형변화 특성도 연구 되었으며, metal line별(別) 전기적 연속, 불연속 배선 단락 특성(electrical continuity test) 관찰도 있었다.

• Transactions on Electrical and Electronic Materials
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• 제8권3호
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• pp.110-114
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• 2007

Dependence of the thermal stability of nickel silicide on the film stress of inter layer dielectric (ILD) layer has been investigated in this study and silicon nitride $(Si_3N_4)$ layer is used as an ILD layer. Nickel silicide was formed with a one-step rapid thermal process at $500^{\circ}C$ for 30 sec. $2000{\AA}$ thick $Si_3N_4$ layer was deposited using plasma enhanced chemical vapor deposition after the formation of Ni silicide and its stress was split from compressive stress to tensile stress by controlling the power of power sources. Stress level of each stress type was also split for thorough analysis. It is found that the thermal stability of nickel silicide strongly depends on the stress type as well as the stress level induced by the $Si_3N_4$ layer. In the case of high compressive stress, silicide agglomeration and its phase transformation from the low-resistivity nickel mono-silicide to the high-resistivity nickel di-silicide are retarded, and hence the thermal stability is obviously improved a lot. However, in the case of high tensile stress, the thermal stability shows the worst case among the stressed cases.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2015년도 제49회 하계 정기학술대회 초록집
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• pp.235.2-235.2
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• 2015

The front transparent conductive oxide (TCO) films must exhibit good transparency, low resistivity and excellent light scattering properties for high efficiency amorphous silicon (a-Si) thin film solar cells. The light trapping phenomenon is limited due to non-uniform and low aspect ratio of the textured glass [1]. We present the low cost electrochemically deposited uniform zinc oxide (ZnO) nanorods with various aspect ratios for a-Si thin film solar cells. Since the major drawback of the electrochemically deposited ZnO nanorods was the high sheet resistance and low transmittance that was overcome by depositing the RF magnetron sputtered AZO films as a seed layer with various thicknesses [2]. The length and diameters of the ZnO nanorods was controlled by varying the deposition conditions. The length of ZnO nanorods were varied from 400 nm to $2{\mu}m$ while diameter was kept higher than 200 nm to obtain different aspect ratios. The uniform ZnO nanorods showed higher haze ratio as compared to the commercially available FTO films. We also observed that the scattering in the longer wavelength region was favored for the high aspect ratio of ZnO nanorods and much higher aspect ratios degraded the light scattering phenomenon. Therefore, we proposed our low cost and uniform ZnO nanorods for the high efficiency of thin film solar cells.

• 한국태양에너지학회:학술대회논문집
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• 한국태양에너지학회 2009년도 춘계학술발표대회 논문집
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• pp.214-219
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• 2009

In high-efficiency crystalline silicon solar cells, If high-efficiency solar cells are to be commercialized. It is need to develop superior contact formation method and material that can be inexpensive and simple without degradation of the solar cells ability. For reason of plated metallic contact is not only high metallic purity but also inexpensive manufacture. It is available to apply mass production. Especially, Nickel, Copper and Silver are applied widely in various electronic manufactures as easily formation is available by plating. The metallic contact system of silicon solar cell must have several properties, such as low contact resistance, easy application and good adhesion. Ni is shown to be a suitable barrier to Cu diffusion as well as desirable contact metal to silicon. Nickel monosilicide(NiSi) has been suggested as a suitable silicide due to its lower resistivity, lower sintering temperature and lower layer stress than $TiSi_2$. Copper and Silver can be plated by electro & light-induced plating method. Light-induced plating makes use the photovoltaic effect of solar cell to deposite the metal on the front contact. The cell is immersed into the electrolytic plating bath and irradiated at the front side by light source, which leads to a current density in the front side grid. Electroless plated Ni/ Electro&light-induced plated Cu/ Light-induced plated Ag contact solar cells result in an energy conversion efficiency of 14.68 % on $0.2{\sim}0.6{\Omega}{\cdot}cm,\;20{\times}20mm^2$, CZ(Czochralski) wafer.