• Title/Summary/Keyword: Low-power transceiver

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A Low Power smartRF Transceiver Hardware Design For 2.4 GHz Applications

  • Kim, Jung-Won;Choi, Ung-Se
    • Journal of IKEEE
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    • v.12 no.2
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    • pp.75-80
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    • 2008
  • There are many researches to reduce power consumption of battery-operated Transceiver for 2.4 GHz smartRF applications. However, components such as processor, memory and LCD based power managements reach the limit of reducing power consumption. To overcome the limit, this research proposes novel low-power Transceiver and transceiver Hardware Design. Experimental results in the real smartRF Transceiver show that the proposed methods can reduce power consumption additionally than component based power managements.

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Low-Power Direct Conversion Transceiver for 915 MHz Band IEEE 802.15.4b Standard Based on 0.18 ${\mu}m$ CMOS Technology

  • Nguyen, Trung-Kien;Le, Viet-Hoang;Duong, Quoc-Hoang;Han, Seok-Kyun;Lee, Sang-Gug;Seong, Nak-Seon;Kim, Nae-Soo;Pyo, Cheol-Sig
    • ETRI Journal
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    • v.30 no.1
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    • pp.33-46
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    • 2008
  • This paper presents the experimental results of a low-power low-cost RF transceiver for the 915 MHz band IEEE 802.15.4b standard. Low power and low cost are achieved by optimizing the transceiver architecture and circuit design techniques. The proposed transceiver shares the analog baseband section for both receive and transmit modes to reduce the silicon area. The RF transceiver consumes 11.2 mA in receive mode and 22.5 mA in transmit mode under a supply voltage of 1.8 V, in which 5 mA of quadrature voltage controlled oscillator is included. The proposed transceiver is implemented in a 0.18 ${\mu}m$ CMOS process and occupies 10 $mm^2$ of silicon area.

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A Fully-Integrated Low Power K-band Radar Transceiver in 130nm CMOS Technology

  • Kim, Seong-Kyun;Cui, Chenglin;Kim, Byung-Sung;Kim, SoYoung
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.12 no.4
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    • pp.426-432
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    • 2012
  • A fully-integrated low power K-band radar transceiver in 130 nm CMOS process is presented. It consists of a low-noise amplifier (LNA), a down-conversion mixer, a power amplifier (PA), and a frequency synthesizer with injection locked buffer for driving mixer and PA. The receiver front-end provides a conversion gain of 19 dB. The LNA achieves a power gain of 15 dB and noise figure of 5.4 dB, and the PA has an output power of 9 dBm. The phase noise of VCO is -90 dBc/Hz at 1-MHz offset. The total dc power dissipation of the transceiver is 142 mW and the size of the chip is only $1.2{\times}1.4mm^2$.

Design and Fabrication of the Transceiver with 400MHz Bandwidth (400 MHz 대역의 송수신기 설계 및 제작)

  • Hur Chang-Wu;Choi Jun-Su
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.10 no.5
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    • pp.851-856
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    • 2006
  • This paper studies about design of a transceiver using a single PLL. The transceiver has bandwidth of $424.7\sim424.95MHz$ and the communication method used 21 channels 12.5 KHz channel bandwidth and FSK modulation/demodulation method. Also, we designed low power wireless transceiver for data transmission using a single PLL. Finally, the transceiver set achieves the following characteristics : 8.15dBm output power, 45.97dBc spurious property.

A 6 Gbps/pin Low-Power Half-Duplex Active Cross-Coupled LVDS Transceiver with Switched Termination

  • Kim, Su-A;Kong, Bai-Sun;Lee, Chil-Gee;Kim, Chang-Hyun;Jun, Young-Hyun
    • ETRI Journal
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    • v.30 no.4
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    • pp.612-614
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    • 2008
  • A novel linear switched termination active cross-coupled low-voltage differential signaling (LVDS) transceiver operating at 1.5 GHz clock frequency is presented. On the transmitter side, an active cross-coupled linear output driver and a switched termination scheme are applied to achieve high speed with low current. On the receiver side, a shared pre-amplifier scheme is employed to reduce power consumption. The proposed LVDS transceiver implemented in an 80 nm CMOS process is successfully demonstrated to provide a data rate of 6 Gbps/pin, an output data window of 147 ps peak-to-peak, and a data swing of 196 mV. The power consumption is measured to be 4.2 mW/pin at 1.2 V.

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Design and Fabrication of Low Power Sensor Network Platform for Ubiquitous Health Care

  • Lee, Young-Dong;Jeong, Do-Un;Chung, Wan-Young
    • 제어로봇시스템학회:학술대회논문집
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    • 2005.06a
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    • pp.1826-1829
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    • 2005
  • Recent advancement in wireless communications and electronics has enabled the development of low power sensor network. Wireless sensor network are often used in remote monitoring control applications, health care, security and environmental monitoring. Wireless sensor networks are an emerging technology consisting of small, low-power, and low-cost devices that integrate limited computation, sensing, and radio communication capabilities. Sensor network platform for health care has been designed, fabricated and tested. This system consists of an embedded micro-controller, Radio Frequency (RF) transceiver, power management, I/O expansion, and serial communication (RS-232). The hardware platform uses Atmel ATmega128L 8-bit ultra low power RISC processor with 128KB flash memory as the program memory and 4KB SRAM as the data memory. The radio transceiver (Chipcon CC1000) operates in the ISM band at 433MHz or 916MHz with a maximum data rate of 76.8kbps. Also, the indoor radio range is approximately 20-30m. When many sensors have to communicate with the controller, standard communication interfaces such as Serial Peripheral Interface (SPI) or Integrated Circuit ($I^{2}C$) allow sharing a single communication bus. With its low power, the smallest and low cost design, the wireless sensor network system and wireless sensing electronics to collect health-related information of human vitality and main physiological parameters (ECG, Temperature, Perspiration, Blood Pressure and some more vitality parameters, etc.)

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Implementation of low power algorithm for near distance wireless communication and RFID/USN systems

  • Kim, Song-Ju;Hwang, Moon-Soo;Kim, Young-Min
    • International Journal of Contents
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    • v.7 no.1
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    • pp.1-7
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    • 2011
  • A new power control algorithm for wireless communication which can be applied to various near distance communications and USN/RFID systems is proposed. This technique has been applied and tested to lithium coin battery operated UHF/microwave transceiver systems to show extremely long communication life time without battery exchange. The power control algorithm is based on the dynamic prediction method of arrival time for incoming packet at the receiver. We obtain 16mA current consumption in the TX module and 20mA current consumption in the RX module. The advantage provided by this method compared to others is that both master transceiver and slave transceiver can be low power consumption system.

A Low Power Consumption 2.4 GHz Transceiver MMIC (저전력소모2.4 GHz 송수신 MMIC)

  • 황인덕
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.36D no.5
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    • pp.1-10
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    • 1999
  • A low power concumption 2.4 GHz one-chip transceiver MMIC was designed and fabricated using $1.0\mu\textrm{m}$ ion-implantation MESFET process and packaged on a 24 lead SSOP. In the transmitter mode, it revealed conversion gain of 7.5 dB, output IP3 of -3.5 dBm, and noise figure of 3.9 dB at 2.44 GHz with 3.9 mA current consumption. In the receiver mode, it revealed voltage sensitivity of 6.5 mV/$\mu\$W with 2 .0 mA current consumption. Comparing the fabricated MMIC with the results of MMICs reported elsewhere, it was shown that the fabricated MMIC had good performance. The low power consumption 2.4 GHz transceiver MMIC is expected to be used for various applications such as wireless local area networks, wireless local loops and RFID tags in ISM-band.

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Implementation of a CMOS RF Transceiver for 900MHz ZigBee Applications (ZigBee 응용을 위한 900MHz CMOS RF 송.수신기 구현)

  • Kwon, J.K.;Park, K.Y.;Choi, Woo-Young;Oh, W.S.
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.43 no.11 s.353
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    • pp.175-184
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    • 2006
  • In this paper, we describe a 900MHz CMOS RF transceiver using an ISM band for ZigBee applications. The architecture of the designed rx front-end, which consists of a low noise amplifier, a down-mixer, a programmable gain amplifier and a band pass filter. And the tx front-end, which consists of a band pass filter, a programmable gain amplifier, an up-mixer and a drive amplifier. A low-if topology is adapted for transceiver architecture, and the total current consumption is reduced by using a low power topology. Entire transceiver is verified by means of post-layout simulation and is implemented in 0.18um RF CMOS technology. The fabricated chip demonstrate the measured results of -92dBm minimum rx input level and 0dBm maximum tx output level. Entire power consumption is 32mW(@1.8VDD). Die area is $2.3mm{\times}2.5mm$ including ESD protection diode pads.

A Design of Transceiver Module for Wire and Wireless Robust Security System (로버스트 유무선 보안시스템을 위한 송수신 모듈의 설계)

  • Park, Sung Geoul;Lee, Jae Min
    • Journal of Digital Contents Society
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    • v.17 no.3
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    • pp.173-180
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    • 2016
  • In this paper, a design of transceiver module for real-time wire and wireless robust integrated security system to solve the problem of conventional security system and its transceiver module is proposed. The presented robust integrated security system is designed with RF control unit and wireless transceiver module. A RF controller in transceiver module works as a low-power RF transceiver system. It is designed to use specific bandwidth stored in registers and manipulate RF power of transceiver by accessing the random values of registers. Operation algorithm for RF transceiver module is also presented. The designed transceiver module and the operation algorithm are implemented and verified by experiments.