• Journal of the Semiconductor & Display Technology
• /
• v.22 no.4
• /
• pp.81-86
• /
• 2023

Recently, demand for embedded systems requiring low power and high specifications has been increasing, and RISC-V processors are being widely applied. RISC-V, a RISC-based open instruction set architecture (ISA), has been developed and researched by UC Berkeley and other researchers since 2010. RV32I ISA is sufficient to support integer operations such as addition and subtraction instructions, but M-extension should be defined for multiplication and division instructions. This paper proposes an RV32I, RV32IM processor, and indicates benchmark performance scores compared to an existing processor. Additionally, A non-stalling method was proposed to support a 2-stage pipelined DSP multiplier to the 5-stage pipelined RV32IM processor. Proposed RV32I and RV32IM processors satisfied a maximum operating frequency of 50 MHz on Artix-7 FPGA. The performance of the proposed processors was verified using benchmark programs from Dhrystone and Coremark. As a result, the Coremark benchmark results of the proposed processor showed that it outperformed the existing RV32IM processor by 23.91%.

• Journal of the Semiconductor & Display Technology
• /
• v.23 no.3
• /
• pp.7-13
• /
• 2024

With the development of technologies such as the Internet of Things (IoT) and autonomous vehicles, research is being conducted on embedded processors that meet high performance, low power, and memory efficiency. The "C" expansion of the RISC-V processor is required to increase memory efficiency. In this paper, we propose an RV32IC processor and compare the benchmark performance score of the RV32I processor with the code size generated by the GCC compiler. In addition, we propose memory access and combination methods to support 16-bit compression commands, and command extension methods. The proposed RV32IC processor satisfies the maximum operating frequency of 50 MHz on the Artix-7 FPGA. The performance was checked using the benchmark programs of the Dhrystone and Coremark, and the code sizes of the RV32I and RV32IC generated by the GCC compiler were compared. The proposed processor RV32IC decreased DMIPS/MHz by 2.72% and Coremark/MHz by 0.61% compared to RV32I, but Coremark's code size decreased by 14.93%.

• Journal of Power Electronics
• /
• v.16 no.6
• /
• pp.2306-2314
• /
• 2016

Design and implementation of a low cost grid-connected 5kVA solar photovoltaic (PV) system is proposed in this paper. Since the inverter is a major component of the PV system, the B4 inverter used in this paper reduces the total cost of the PV system. In order to eliminate the massive transformer, the PV system is connected to the grid through IGBT switches. In addition to injection of active power into the grid, the B4 inverter can compensate reactive power and reduce harmonics of the nonlinear loads. A TMS320F28335 DSP processor is used for effective control of the B4 inverter. Various features of this processor enable the implementation of the necessary control algorithms. As a first step, the PV system is simulated and evaluated in Matlab/Simulink. In the second step, hardware circuits are designed and implemented based on the simulation results. The operation of the PV system has been evaluated under balanced, unbalanced, linear and nonlinear loads which proves its accuracy and efficiency.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2003.10a
• /
• pp.941-944
• /
• 2003

This paper implement Telemetry System which is used Bluetooth. This System propose system which can detect a total amount of gas, electricity or water without a motorman, at home. BlueTooth is a close range wireless communication technology which uses a wireless frequency 2.4GHz and has a high trust and self - error correction technology according to a low power consumption quality and a high-speed frequency hopping. This makes get a high trust concerning a data transmission than an existing modem. In addition, though wireless modem is restricted by a minimal of a wireless terminal, it will be possible to coincide with the function of the portable with the low power consumption quality by using Bluetooth. And as the system on a chip of module progresses, the possibility of the snail size is present. And, Motorman who use mobility of embedded system can detect detect a total amount of gas, electricity or water outdoor. Embedded system use ARM processor that is low power processor. So it ran use long time efficiently.

• Proceedings of the KIPE Conference
• /
• 2012.11a
• /
• pp.5-6
• /
• 2012

In this paper, a simplified maximum power point tracking technique for the solar charger is presented. Main advantages of the proposed charger include low cost and optimized charge time. The maximum power point tracking method is used to deliver the maximum power from PV array to the battery thereby reducing the charge time. Moreover, the proposed technique which tracks the maximum power point by adjusting output current helps reduce the quantity of required number of sensors for the charger. The experimental protype was implemented by using an 80W PV array, a buck converter and a digital signal processor to verify the feasibility of the proposed method.

• Proceedings of the IEEK Conference
• /
• 2001.06b
• /
• pp.105-108
• /
• 2001

4 32-bit RISC core is designed for embedded application and DSP. This processor offers low power consumption by fully static operation and compact code size by efficient instruction set. Processor performance is improved by wing conditional instruction execution, block data transfer instruction, multiplication instruction, bunked register file structure. To support compact code size of embedded application, It is capable cf executing both 16-bit instructions and 32-bit instruction through mixed mode instruction conversion Furthermore, for fast MAC operation for DSP applications, the processor has a dedicated hardware multiplier, which can complete a 32-bit by 32-bit integer multiplication within seven clock cycles. These result in high instruction throughput and real-time interrupt response. This chip is implemented with 0.35${\mu}{\textrm}{m}$, 4- metal CMOS technology and consists of about 50K gate equivalents.

• Proceedings of the KIEE Conference
• /
• 2008.10c
• /
• pp.246-247
• /
• 2008

Further evolutions of technologies and needs of users will make mobile equipments improved. To make this happen, processor's good performance is essential. Hence, This paper propose a reform of Instruction Execute and Instruction Decode of contemporary ARMv7 which needs low-power and has the high performance for a faster processor. The first chapter explains why the performance of a processor has to be upgraded, the second chapter shows current technologies. The third chapter explains about the proposal and illustrates the structure. Finally, in the forth chapter, the conclusion will be made. 3-way Superscalar, that is proposed in this paper, will make designing a faster processor possible. And it will contribute for the advanced performance of mobile equipments.

• 제어로봇시스템학회:학술대회논문집
• /
• 2005.06a
• /
• pp.1826-1829
• /
• 2005

Recent advancement in wireless communications and electronics has enabled the development of low power sensor network. Wireless sensor network are often used in remote monitoring control applications, health care, security and environmental monitoring. Wireless sensor networks are an emerging technology consisting of small, low-power, and low-cost devices that integrate limited computation, sensing, and radio communication capabilities. Sensor network platform for health care has been designed, fabricated and tested. This system consists of an embedded micro-controller, Radio Frequency (RF) transceiver, power management, I/O expansion, and serial communication (RS-232). The hardware platform uses Atmel ATmega128L 8-bit ultra low power RISC processor with 128KB flash memory as the program memory and 4KB SRAM as the data memory. The radio transceiver (Chipcon CC1000) operates in the ISM band at 433MHz or 916MHz with a maximum data rate of 76.8kbps. Also, the indoor radio range is approximately 20-30m. When many sensors have to communicate with the controller, standard communication interfaces such as Serial Peripheral Interface (SPI) or Integrated Circuit ($I^{2}C$) allow sharing a single communication bus. With its low power, the smallest and low cost design, the wireless sensor network system and wireless sensing electronics to collect health-related information of human vitality and main physiological parameters (ECG, Temperature, Perspiration, Blood Pressure and some more vitality parameters, etc.)

• The Transactions of the Korean Institute of Power Electronics
• /
• v.6 no.1
• /
• pp.27-33
• /
• 2001

This paper presents a digital instrument for a DSP based power quality analysis in three phase power system where current waveform is non-sinusoidal. it is based on stand alone type TMS320C31 DSP(digital signal processor)board and on a special high-speed data acquisition system. Power quality of low power motor drives are analyzed and processed by using a simple average power algorithm, and result of power analysis are displayed by LCD in the proposed system. This paper also goes on to discuss the performance of an instrument prototype, both in terms of accuracy and speed of measurement under the transient and steady state condition.

• Journal of the Korea Society of Computer and Information
• /
• v.15 no.1
• /
• pp.1-12
• /
• 2010

Recently, processor performance has been improved dramatically. Unfortunately, as the process technology scales down, energy consumption in a processor increases significantly whereas the processor performance continues to improve. Moreover, peak temperature in the processor increases dramatically due to the increased power density, resulting in serious thermal problem. For this reason, performance, energy consumption and thermal problem should be considered together when designing up-to-date processors. This paper proposes three modified filter cache schemes to alleviate the thermal problem in the filter cache, which is one of the most energy-efficient design techniques in the hierarchical memory systems : Bypass Filter Cache (BFC), Duplicated Filter Cache (DFC) and Partitioned Filter Cache (PFC). BFC scheme enables the direct access to the L1 cache when the temperature on the filter cache exceeds the threshold, leading to reduced temperature on the filter cache. DFC scheme lowers temperature on the filter cache by appending an additional filter cache to the existing filter cache. The filter cache for PFC scheme is composed of two half-size filter caches to lower the temperature on the filter cache by reducing the access frequency. According to our simulations using Wattch and Hotspot, the proposed partitioned filter cache shows the lowest peak temperature on the filter cache, leading to higher reliability in the processor.