• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.61-66
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• 2008

Recently, portable devices which require small area and low power consumption employ applications using 3D graphics such as 3D games and 3D graphical user interfaces. We propose an efficient clipping engine algorithm which is suitable in 3D graphics pipeline. The clipping operation is divided into two steps: one is the selection process in the transformation engine and the other is the pixel clipping process in the scan conversion unit. The clipping operation is possible with addition of simple comparator. The clipping for the Y-axis is achieved in the edge walk stage and that for the X and Z-axis is performed in the span processing. The proposed clipping algorithm reduces the operation cycles and the area of of 3D graphics pipelines. We designed a 3D graphics pipeline with the proposed clipping algorithm using Verilog-HDL and verifies the operation using an FPGA.

• 한국ITS학회:학술대회논문집
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• v.2007 no.10
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• pp.225-229
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• 2007

Recently, wireless sensor networks are deployed in various applications range from simple environment monitoring systems to complex systems, which generate large amount of information, like motion monitoring, military, and telematics systems. Although wireless sensor network nodes are operated with low-power 8bit processor to execute simple tasks like environment monitoring, the nodes in these complex systems have to execute more difficult tasks. Generally, MAC protocols for wireless sensor networks attempt to reduce the energy consumption using duty cycling mechanism which means the nodes periodically sleep and wake. However, in the duty cycling mechanism. a node should wait until the target node wakes and the sleep latency increases as the number of hops increases. This sleep latency can be serious problem in complex and sensitive systems which require high speed data transfer like military, wing of airplane, and telematics. In this paper, we propose a solution for reducing transmission latency through distributed duty cycling (DDC) in wireless sensor networks. The proposed algorithm is evaluated with real-deployment experiments using CC2420DBK and the experiment results show that the DDC algorithm reduces the transmission latency significantly and reduces also the energy consumption.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.24-30
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• 2009

In this paper, the FPGA modem platform complying with 3GPP Release 7 eHSPA specifications and its regularized verification flow are proposed. The FFGA platform consists of modem board supporting physical layer requirements, MCU and DSP core embedded control board to drive the modem board, and peripheral boards for RF interfacing and various equipment interfaces. On the other hand, the proposed verification flow has been regularized into three categories according to the correlation degrees of hardware-software inter-operation, such as simple function test, scenario test call processing and system-level performance test. When it comes to real implementations, the emulation verification strategy for low power mobile SoC is also introduced.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.6
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• pp.895-902
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• 2018

Energy consumption in buildings is close to 40% of the total national energy consumption in developed countries such as US and Japan, and Korea accounts for 24% of total energy consumption. In buildings, HVAC can't freely control the cooling flow rate according to the required calorie, so energy is not used efficiently. Therefore, by using the energy saving valve, the flow rate can be controlled by the required amount of heat and the energy can be saved. In this paper, we define basic conditions and develop control and monitoring boards for building energy saving valves based on PIC processor with low power and high cost-effectiveness. The designed board displays and transmits in real time information about two temperature values, flow values and calculated calories for temperature difference measurement. The developed board will be useful for real - time monitoring of the state of the valve in the future and development of the valve for the offshore.

• KIEE International Transactions on Power Engineering
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• v.5A no.2
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• pp.116-124
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• 2005

This paper presents an application of the parallel Genetic Algorithm-Tabu Search (GA- TS) algorithm, and that is to search for an optimal solution of a reconfiguration in distribution systems. The aim of the reconfiguration of distribution systems is to determine the appropriate switch position to be opened for loss minimization in radial distribution systems, which is a discrete optimization problem. This problem has many constraints and it is very difficult to solve the optimal switch position because of its numerous local minima. This paper develops a parallel GA- TS algorithm for the reconfiguration of distribution systems. In parallel GA-TS, GA operators are executed for each processor. To prevent solution of low fitness from appearing in the next generation, strings below the average fitness are saved in the tabu list. If best fitness of the GA is not changed for several generations, TS operators are executed for the upper 10$\%$ of the population to enhance the local searching capabilities. With migration operation, the best string of each node is transferred to the neighboring node after predetermined iterations are executed. For parallel computing, we developed a PC-cluster system consisting of 8 PCs. Each PC employs the 2 GHz Pentium IV CPU and is connected with others through switch based rapid Ethernet. To demonstrate the usefulness of the proposed method, the developed algorithm was tested and is compared to a distribution system in the reference paper From the simulation results, we can find that the proposed algorithm is efficient and robust for the reconfiguration of distribution system in terms of the solution quality, speedup, efficiency, and computation time.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.257-260
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• 2002

This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm“Rijndael”. To achieve high throughput rate, a sub-pipeline stage is inserted into the round transformation block, resulting that the second half of current round function and the first half of next round function are being simultaneously operated. For area-efficient and low-power implementation the round transformation block is designed to share the hardware resources in encryption and decryption. An efficient scheme for on-the-fly key scheduling, which supports the three master-key lengths of 128-b/192-b/256-b, is devised to generate round keys in the first sub-pipeline stage of each round processing. The cryptoprocessor designed in Verilog-HDL was verified using Xilinx FPGA board and test system. The core synthesized using 0.35-${\mu}{\textrm}{m}$ CMOS cell library consists of about 25,000 gates. Simulation results show that it has a throughput of about 520-Mbits/sec with 220-MHz clock frequency at 2.5-V supply.

• The KIPS Transactions:PartA
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• v.14A no.1 s.105
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• pp.55-62
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• 2007

Uptime of embedded processors for mobile devices are dependent on battery consumption. Especially the large portion of power consumption is known to be due to cache management in embedded processors. This paper proposes an energy efficient data cache structure for high performance embedded processors. High performance prefetching data cache issues prefetching instructions before issuing demand-fetch instructions based on reference predictions. These prefetching instruction bring reduction on memory delay by improving cache hit ratio, but on the other hand those increase energy consumption in proportion to the number of prefetching instructions. In this paper, we adopt tag history table on prefetching data cache for reducing energy consumption by minimizing parallel tag comparison. Experimental results show the proposed data cache improves performance on energy consumption as well as memory delay.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.33-43
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• 2002

This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm "Rijndael". To achieve high throughput rate, a sub-pipeline stage is inserted into a round transformation block, resulting that two consecutive round functions are simultaneously operated. For area-efficient and low-power implementation, the round transformation block is designed to share the hardware resources for encryption and decryption. An efficient on-the-fly key scheduler is devised to supports the three master-key lengths of 128-b/192-b/256-b, and it generates round keys in the first sub-pipeline stage of each round processing. The Verilog-HDL model of the cryptoprocessor was verified using Xilinx FPGA board and test system. The core synthesized using 0.35-${\mu}m$ CMOS cell library consists of about 25,000 gates. Simulation results show that it has a throughput of about 520-Mbits/sec with 220-MHz clock frequency at 2.5-V supply.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.45 no.3
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• pp.103-110
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• 2008

In this paper, an efficient butterfly structure for 8K/2K-Point Radix-4 FFT algorithm using CORDIC(coordinate rotation digital computer) is proposed. It is shown that CORDIC can be efficiently used in twiddle factor calculation of the Radix-4 FFT algorithm. The Verilog-HDL coding results for the proposed CORDIC butterfly structure show 36.9% cell area reduction comparison with those of the conventional multiplier butterfly structure. Furthermore, the 8K/2K-point Radix-4 pipeline structure using the proposed butterfly and delay commutators is compared with other conventional structures. Implementation coding results show 11.6% cell area reduction. Due to its efficient processing scheme, the proposed FFT structure can be widely used in large size of FFT like OFDM Modem.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.9 no.4
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• pp.39-45
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• 2009

With the rapid growth of recent wireless mobile computing application technology and handheld mobile terminal device development technology, one of the big issue in these fields is to design online games in wireless mobile ad hoc network environment. Online games in mobile computing environment have lots of constraints for developing online games because mobile terminals have many limitations such as low performance of processor, limited memory space, small bandwidth of wireless communication, and confined life of battery power. Therefore, most of mobile games are restrictive in the function of online and multi-play up to date. In this paper, the online MMORPG game, capable of multi-play with many other mobile users using mobile terminals in wireless mobile computing environment, is designed and implemented. Proposed mobile online game uses bluetooth to construct temporary wireless mobile ad hoc network with other mobile clients, and designed to carry out online MMORPG game with these clients. It also supports multi-play among them.