• Title/Summary/Keyword: Low-power processor

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Simulation of YUV-Aware Instructions for High-Performance, Low-Power Embedded Video Processors (고성능, 저전력 임베디드 비디오 프로세서를 위한 YUV 인식 명령어의 시뮬레이션)

  • Kim, Cheol-Hong;Kim, Jong-Myon
    • Journal of KIISE:Computing Practices and Letters
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    • v.13 no.5
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    • pp.252-259
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    • 2007
  • With the rapid development of multimedia applications and wireless communication networks, consumer demand for video-over-wireless capability on mobile computing systems is growing rapidly. In this regard, this paper introduces YUV-aware instructions that enhance the performance and efficiency in the processing of color image and video. Traditional multimedia extensions (e.g., MMX, SSE, VIS, and AltiVec) depend solely on generic subword parallelism whereas the proposed YUV-aware instructions support parallel operations on two-packed 16-bit YUV (6-bit Y, 5-bits U, V) values in a 32-bit datapath architecture, providing greater concurrency and efficiency for color image and video processing. Moreover, the ability to reduce data format size reduces system cost. Experiment results on a representative dynamically scheduled embedded superscalar processor show that YUV-aware instructions achieve an average speedup of 3.9x over the baseline superscalar performance. This is in contrast to MMX (a representative Intel#s multimedia extension), which achieves a speedup of only 2.1x over the same baseline superscalar processor. In addition, YUV-aware instructions outperform MMX instructions in energy reduction (75.8% reduction with YUV-aware instructions, but only 54.8% reduction with MMX instructions over the baseline).

Energy-Efficient Signal Processing Using FPGAs (FPGA 상에서 에너지 효율이 높은 병렬 신호처리 기법)

  • Jang Ju-wook;Hwang Yunil;Scrofano Ronald;Prasanna Viktor K.
    • The KIPS Transactions:PartA
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    • v.12A no.4 s.94
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    • pp.305-312
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    • 2005
  • In this paper, we present algorithm-level techniques for energy-efficient design at the algorithm level using FPGAs. We then use these techniques to create energy-efficient designs for two signal processing kernel applications: fast Fourier transform(FFT) and matrix multiplication. We evaluate the performance, in terms of both latency and energy efficiency, of FPGAs in performing these tasks. Using a Xilinx Virtex-II as the target FPGA, we compare the performance of our designs to those from the Xilinx library as well as to conventional algorithms run on the PowerPC core embedded in the Virtex-II Pro and the Texas Instruments TMS320C6415. Our evaluations are done both through estimation based on energy and latency equations on high-level and through low-level simulation. For FFT, our designs dissipated an average of $50\%$ less energy than the design from the Xilinx library and $56\%$ less than the DSP. Our designs showed an EAT factor of 10 times improvement over the embedded processor. These results provide a concrete evidence to substantiate the idea that FPGAs can outperform DSPs and embedded processors in signal processing. Further, they show that PFGAs can achieve this performance while still dissipating less energy than the other two types of devices.

Low Power EccEDF Algorithm for Real-Time Operating Systems (실시간 운영체제를 위한 저전력 EccEDF 알고리듬)

  • Lee, Min-Seok;Lee, Cheol-Hoon
    • The Journal of the Korea Contents Association
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    • v.15 no.1
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    • pp.31-43
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    • 2015
  • For battery based real-time embedded systems, high performance to meet their real-time constraints and energy efficiency to extend battery life are both essential. Real-Time Dynamic Voltage Scaling (RT-DVS) has been a key technique to satisfy both requirements. In this paper, we present an efficient RT-DVS algorithm called EccEDF that is designed based on ccEDF. The proposed algorithm can precisely calculate the maximum unused utilization with consideration of the elapsed time while keeping the structural simplicity of ccEDF, which overlooked the time needed to run the task in calculating the available slack. The maximum unused utilization can be calculated by dividing remaining execution time($C_i-cc_i$) by remaining time($P_i-E_i$) on completion of the task and it is proved using Fluid scheduling model. We also show that the algorithm outperforms ccEDF in practical applications which is modelled using a PXA250 and a 0.28V-to-1.2V wide-operating-range IA-32 processor model.

Development of Embedded X-System (임베디드 X-시스템 개발)

  • Jeong, Gab-Joong
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2008.05a
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    • pp.641-644
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    • 2008
  • This paper describes the GUI implementation of an intelligent embedded system which can be used for a personal information platform and an industrial mobile application system. It shows the architecture and the necessary structure and components of X Window graphic system. The embedded system used in this paper has low power and high performance processor, and has a large memory size with a nand-flash memory device. We configured the linux kernel with a TIT-LCD and touch screen device for the operation of X Window system. And we used GTK+2 for running application softwares on the platform embedded system. The GUI library of GTK+2 is useful for providing the same graphics programming environment with host Linux PC. We have developed in this paper the X Window system and the GUI environment for GTK+2 in a new embedded system, and verified the full operation of X Window system and application softwares using GTK+2. The embedded system with large memory size can be used in X Window application softwares for providing a personal information service with a mobile embedded system.

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Using High Brightness LED Light Source Controller for Machine Vision (고휘도 LED를 이용한 머신비전용 조명광원 제어기 개발)

  • Park, Yang-Jae
    • Journal of Digital Convergence
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    • v.12 no.4
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    • pp.311-318
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    • 2014
  • This paper is to introduce a lighting source controller using high brightness LED to create a clear and reliable condition for an accurate measurement and testing, which is a core technology in clinical image system and mechanical automation system. This controller is designed to supply a stable power in a constant-current system by installing a high brightness LED driver, and to improve the reproducibility of brightness by using 32-bit ARM processor core, dividing brightness quantity into 256 levels, making the remote control and the external interface possible, and preventing and digitizing the brightness inaccuracy caused by errors of resistance values. This controller enables the lighting range to be wide and possible in a low lighting level compared to analog, adds the RS-485 communication function, and makes it for the users to control the on-off function and the dimming level by receiving date from an external device.

Design of a 3D Graphics Geometry Accelerator using the Programmable Vertex Shader (Programmable Vertex Shader를 내장한 3차원 그래픽 지오메트리 가속기 설계)

  • Ha Jin-Seok;Jeong Hyung-Gi;Kim Sang-Yeon;Lee Kwang-Yeob
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.9 s.351
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    • pp.53-58
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    • 2006
  • A Vertex Shader is designed to show more 3D graphics expressions, and to increase flexibility of the fixed function T&L (Transform and Lighting) engine. Design of this Shader is based on Vertex Shader 1.1 of DirectX 8.1 and OpenGL ARB. The Vertex Shader consists of four floating point ALUs for vectors operation. The previous 32bits floating point data type is replaced to 24bits floating point data type in order to design the Vertex Shader that consume low-power and occupy small area. A Xilinx Virtex2 300M gate module is used to verify behaviour of the core. The result of Synopsys synthesis shows that the proposed Vertex Shader performs 115MHz speed at the TSMC 0.13um process and it can operate as the rate of 12.5M Polygons/sec. It shows the complexity of 110,000 gates in the same process.

Design and Analysis of a $AB^2$ Systolic Arrays for Division/Inversion in$GF(2^m)$ ($GF(2^m)$상에서 나눗셈/역원 연산을 위한 $AB^2$ 시스톨릭 어레이 설계 및 분석)

  • 김남연;고대곤;유기영
    • Journal of KIISE:Computer Systems and Theory
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    • v.30 no.1
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    • pp.50-58
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    • 2003
  • Among finite field arithmetic operations, the $AB^2$ operation is known as an efficient basic operation for public key cryptosystems over $GF(2^m)$,Division/Inversion is computed by performing the repetitive AB$^2$ multiplication. This paper presents two new $AB^2$algorithms and their systolic realizations in finite fields $GF(2^m)$.The proposed algorithms are based on the MSB-first scheme using standard basis representation and the proposed systolic architectures for $AB^2$ multiplication have a low hardware complexity and small latency compared to the conventional approaches. Additionally, since the proposed architectures incorporate simplicity, regularity, modularity, and pipelinability, they are well suited to VLSI implementation and can be easily applied to inversion architecture. Furthermore, these architectures will be utilized for the basic architecture of crypto-processor.

A Design of Power Converter for Fuel Cell Controlled by Micro-Processor (마이크로프로세서에 의해 제어되는 연료전지용 전력변환 회로 설계)

  • Won, Chung-Yuen;Jang, Su-Jin;Lee, Won-Chul;Lee, Tae-Won;Kim, Soo-Seok
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.18 no.5
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    • pp.61-68
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    • 2004
  • Recently, a fuel cell is remarkable for new generation system. The fuel cell is characterized by low voltage and high current. Therefor, for connecting to general load, it needs both a step up converter and an inverter. The proposed system consists of an isolated DC-DC converter to boost the fuel cell voltage to 380[Vdc] and a PWM inverter with LC filter to convert the dc voltage to single phase 220[Vac]. Also, bi-directional DC-DC converter for fuel cell generation system is composed to improve load response characteristic. In this paper, full bridge converter and the single phase inverter are designed and installed for fuel cell. Simulation and experiment verify that fuel cell generation system could be applied for the distributed generation.

A Study on the Implementation of Embedded DHCP Server Based on ARM (ARM 기반의 임베디드 DHCP서버 구축에 관한 연구)

  • Kim Hyeong-Gyun;Lee Sang-Beom
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.10 no.8
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    • pp.1490-1494
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    • 2006
  • Most network equipment is an embedded system designed to execute specific function. An embedded system is an electronic control system mixing hardware and software to execute only fixed function for the purpose of system, not confuter, performing diverse function for a wide use. Early embedded system executed only simple function, combining specific function with optimization, a micro size, and low power, but it has developed to meet complex and diverse system. The purpose of this study is to realize DHCP server based on embedded system. To achieve this, embedded Linux was ported in ez Bord-M01 mounted with Intel Strong ARM SA1110 processor, and ethernet-based network was constructed for network function. In this way, this study suggests embedded DHCP server where Window and Linux client hosts are dynamically configurated as network information by dynamically assigning network information in embedded board.

A High Performance Transmission Method for Massively Delivering Multimedia Data in WMSN (무선 멀티미디어 센서 네트워크(WMSN) 환경에서 멀티미디어 데이터 전송을 위한 대용량 전송 기법에 대한 연구)

  • Lee, Jae-Ho;Eom, Doo-Seop
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.37A no.11
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    • pp.903-917
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    • 2012
  • For transmitting sensed data, wireless sensor networks have been developed and researched for the improvement of energy efficiency, hence, many MAC protocols in WSN employ the duty cycle mechanism. Since the progressed development of the low power transceiver and processor let the high energy efficiency come true, the delivery of the multimedia data which occurs in area of sensor work should be needed to provide supplemental information. In this paper, we design a new scheme for massive transmission of large multimedia data where the duty cycle is used in contention based MAC protocol, for WMSN. The proposed scheme can be applied into the previous duty cycle mechanism because it provides two operation between normal operation and massive transmission operation. Measuring the buffer status of sender and the condition of current radio channel can be criteria for the decision of the above two operations. This paper shows the results of the experiment by performing the simulation. The target protocol of the experiment is X-MAC which is contention based MAC protocol for WSN. And two approaches, both X-MAC which operates only duty cycle and X-MAC which operates combined massive transmission scheme, are used for the comparative experiment.