• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.06a
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• pp.179-183
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• 2007

This paper is to implement a low power frequency Shift Keying(FSK) receiver using Xilinx System Generator. The receiver incorporates a 16 point Fast Fourier Transform(FFT) for symbol detection. The design units of the receiver are digital designs for better efficiency and reliability. The receiver functions on one bit data processing and supports data rates 10kbps. In addition CORDIC algorithm is used for avoiding complex multiplications while computing FFT, multiplication of twiddle factor is substituted by rotators. The design and simulation of the receiver is carried out in Simulink, then the simulink model is translated to a hardware model to implement FPGA using Xilinx System Generator and to verify performance.

• Journal of the Korean Institute of Telematics and Electronics
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• v.19 no.4
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• pp.38-48
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• 1982

Performance and realization of finite impulse response (FIR) digital filters that use an adaptive delta modulator (ADM) as an analog/digital converter have been studied. This filter requires no multiplication and offers many advantages over conventional PCM filters in low power consumption, small size, and cost effectiveness. Analytical formulas have been derived for the expected mean-squared errors and also for the word length necessary to achieve the desired performance. Computer simultation has been done to optimize the parameter values and to verify the results of performance analysis. In addition, design of FIR ADM digital filters for processing single and multi-channel signals has been considered.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.809-811
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• 2010

In most floating-point operations related with 3D graphic applications for mobile devices, properly approximated data calculations with reduced complexity and low power are preferable to exactly rounded floating-point operations with unnecessary preciseness with cost. Among all the sophisticated floating-point arithmetic operations, multiplication and division are the most complicated and time-consuming, and they can be transformed into addition and subtraction repectively by adopting the logarithmic conversion. In this process, the most important factor for performance is how high we can make an approximation of the logarithm conversion. In this paper, we cover the trends in studying the logarithm conversion circuit designs. We also discuss the important factor in design issues and the applicable fields in detail.

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.81-86
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• 2023

Recently, demand for embedded systems requiring low power and high specifications has been increasing, and RISC-V processors are being widely applied. RISC-V, a RISC-based open instruction set architecture (ISA), has been developed and researched by UC Berkeley and other researchers since 2010. RV32I ISA is sufficient to support integer operations such as addition and subtraction instructions, but M-extension should be defined for multiplication and division instructions. This paper proposes an RV32I, RV32IM processor, and indicates benchmark performance scores compared to an existing processor. Additionally, A non-stalling method was proposed to support a 2-stage pipelined DSP multiplier to the 5-stage pipelined RV32IM processor. Proposed RV32I and RV32IM processors satisfied a maximum operating frequency of 50 MHz on Artix-7 FPGA. The performance of the proposed processors was verified using benchmark programs from Dhrystone and Coremark. As a result, the Coremark benchmark results of the proposed processor showed that it outperformed the existing RV32IM processor by 23.91%.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.16 no.4
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• pp.3-12
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• 2006

RFID (Radio Frequency Identification) system is expected to play a critical role providing widespread services in the ubiquitous period. However, widespread use of RFID tags may create new threats to the privacy of individuals such as information leakage and traceability. It is difficult to solve the privacy problems because a tag has the limited computing power that is not the adequate resource to support the general encryption. Although the scheme of [2] protects the consumer privacy using an external agent, a tag should compute exponential operation needed high cost. We propose Self Re-Encryption Protocol (SREP) which provides song privacy without assisting of any external agent. Our SREP is well suitable to low-cost RFID system since it only needs multiplication and exclusive-or operation.

• The KIPS Transactions:PartA
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• v.12A no.5 s.95
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• pp.451-460
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• 2005

We present a methodology to design energy-efficient data paths using FPGAs. Our methodology integrates domain specific modeling, coarse-grained performance evaluation, design space exploration, and low-level simulation to understand the tradeoffs between energy, latency, and area. The domain specific modeling technique defines a high-level model by identifying various components and parameters specific to a domain that affect the system-wide energy dissipation. A domain is a family of architectures and corresponding algorithms for a given application kernel. The high-level model also consists of functions for estimating energy, latency, and area that facilitate tradeoff analysis. Design space exploration(DSE) analyzes the design space defined by the domain and selects a set of designs. Low-level simulations are used for accurate performance estimation for the designs selected by the DSE and also for final design selection We illustrate our methodology using a family of architectures and algorithms for matrix multiplication. The designs identified by our methodology demonstrate tradeoffs among energy, latency, and area. We compare our designs with a vendor specified matrix multiplication kernel to demonstrate the effectiveness of our methodology. To illustrate the effectiveness of our methodology, we used average power density(E/AT), energy/(area x latency), as themetric for comparison. For various problem sizes, designs obtained using our methodology are on average $25\%$ superior with respect to the E/AT performance metric, compared with the state-of-the-art designs by Xilinx. We also discuss the implementation of our methodology using the MILAN framework.

• Journal of Broadcast Engineering
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• v.27 no.3
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• pp.378-390
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• 2022

With the recent development of deep composite multiplication neural network learning, deep learning techniques applied to single-image super-resolution have shown good results, and the strong expression ability of deep networks has enabled complex nonlinear mapping between low-resolution and high-resolution images. However, there are limitations in applying it to real-time or low-power devices with increasing parameters and computational amounts due to excessive use of composite multiplication neural networks. This paper uses blocks that extract hierarchical characteristics little by little using information distillation and suggests the Recursive Distillation Super Resolution Network (RDSRN), a lightweight network that improves performance by making more accurate high frequency components through high frequency residual purification blocks. It was confirmed that the proposed network restores images of similar quality compared to RDN, restores images 3.5 times faster with about 32 times fewer parameters and about 10 times less computation, and produces 0.16 dB better performance with about 2.2 times less parameters and 1.8 times faster processing time than the existing lightweight network CARN.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.3
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• pp.165-171
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• 2019

The study of the computer architecture has shown that major improvements in price-to-energy performance stems from domain-specific hardware development. This paper analyzes the tensor processing unit (TPU) ASIC which can accelerate the reasoning of the artificial neural network (NN). The core device of the TPU is a MAC matrix multiplier capable of high-speed operation and software-managed on-chip memory. The execution model of the TPU can meet the reaction time requirements of the artificial neural network better than the existing CPU and the GPU execution models, with the small area and the low power consumption even though it has many MAC and large memory. Utilizing the TPU for the tensor flow benchmark framework, it can achieve higher performance and better power efficiency than the CPU or CPU. In this paper, we analyze TPU, simulate the Python modeled OpenTPU, and synthesize the matrix multiplication unit, which is the key hardware.

• Nuclear Engineering and Technology
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• v.54 no.9
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• pp.3516-3525
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• 2022

The high capture cross-section (𝜎_c) of Gadolinium (Gd-155 and Gd-157) causes reactivity penalty and swing at the initial stage of fuel burnup in Pressurized Water Reactor (PWR). The present study is concerned with the feasibility of the combination of mixed burnable poison with both low and high 𝜎_c as an approach to minimize these effects. Two considered reference designs are fuel assemblies with 24 IBA rods of Gd₂O₃ and Er₂O₃ respectively. Models comprise nuclear fuel with a homogeneous mixture of Er₂O₃, AmO₂, SmO₂, and HfO₂ with Gd₂O₃ as well as the coating of PaO₂ and ZrB₂ on the Gd₂O₃ pellet's outer surface. The infinite multiplication factor was determined and reactivity was calculated considering 3% neutron leakage rate. All models except Er₂O₃ and SmO₂ showed expected results namely higher values of these parameters than the reference design of Gd₂O₃ at the early burnup period. The highest value was found for the model of PaO₂ and Gd₂O₃ followed by ZrB₂ and HfO₂. The cycle burnup, discharge burnup, and cycle length for three batch refueling were calculated using Linear Reactivity Model (LRM). The pin power distribution, energy-dependent neutron flux and Fuel Temperature Coefficient (FTC) were also studied. An optimization of model 1 was carried out to investigate effects of different isotopic compositions of Gd₂O₃ and absorber coating thickness.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.400.1-400.1
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• 2016

Interfacial engineering approaches as an efficient strategy for improving the power conversion efficiencies (PCEs) of inverted polymer solar cells (iPSCs) has attracted considerable attention. Recently, polymer surface modifiers, such as poly(ethyleneimine) (PEI) and polyethylenimine ethoxylated (PEIE), were introduced to produce low WF electrodes and were reported to have good electron selectivity for inverted polymer solar cells (iPSCs) without an n-type metal oxide layer. To obtain more efficient solar cells, quantum dots (QDs) are used as effective sensitizers across a broad spectral range from visible to near IR. Additionally, they have the ability to efficiently generate multiple excitons from a single photon via a process called carrier multiplication (CM) or multiple exciton generation (MEG). However, in general, it is very difficult to prepare a bilayer structure with an organic layer and a QD interlayer through a solution process, because most solvents can dissolve and destroy the organic layer and QD interlayer. To present a more effective strategy for surpassing the limitations of traditional methods, we studied and fabricated the highly efficient iPSCs with mono-layered QDs as an effective multi-functional layer, to enhance the quantum yield caused by various effects of QDs monolayer. The mono-layered QDs play the multi-functional role as surface modifier, sub-photosensitizer and electron transport layer. Using this effective approach, we achieve the highest conversion efficiency of ~10.3% resulting from improved interfacial properties and efficient charge transfer, which is verified by various analysis tools.