• Journal of Power Electronics
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• 제17권5호
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• pp.1186-1194
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• 2017

This paper proposes an improved low frequency Selective Harmonic Mitigation-PWM (SHM-PWM) technique. The proposed method mitigates the low order harmonics of the output voltage up to the $50^{th}$ harmonic well and satisfies the grid codes EN 50160 and CIGRE-WG 36-05. Using a modified criterion for the switching angles, the range of the modulation index for non-linear SHM equations is improved, without increasing the switching frequency of the CHB converter. Due to the low switching frequency of the CHB converter, mitigating the harmonics of the converter up to the $50^{th}$ order and finding a wider modulation index range, the size and cost of the passive filters can be significantly reduced with the proposed technique. Therefore, the proposed technique is more efficient than the conventional SHM-PWM. To verify the effectiveness of the proposed method, a 7-level Cascaded H-bridge (CHB) converter is utilized for the study. Simulation and experimental results confirm the validity of the above claims.

• 한국컴퓨터정보학회논문지
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• 제20권11호
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• pp.1-8
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• 2015

Flash memory has advantages in that it is fast access speed, low-power, and low-price. Therefore, they are widely used in electronics industry sectors. However, the flash memory has weak points, which are the limited number of erase operations and non-in-place update problem. To overcome the limited number of erase operations, many wear leveling techniques are studied. They use many tables storing information such as erase count of blocks, hot and cold block indicators, reference count of pages, and so on. These tables occupy some space of main memory for the wear leveling techniques. Accordingly, they are not appropriate for low-power devices limited main memory. In order to resolve it, a wear leveling technique using bit array and Bit Set Threshold (BST) for flash memory. The proposing technique reduces the used space of main memory using a bit array table, which saves the history of block erase operations. To enhance accuracy of cold block information, we use BST, which is calculated by using the number of invalid pages of the blocks in a one-to-many mode, where one bit is related to many blocks. The performance results illustrate that the proposed wear leveling technique improve life time of flash memory to about 6%, compared with previous wear leveling techniques using a bit array table in our experiment.

• Journal of Electrical Engineering and Technology
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• 제1권1호
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• pp.63-72
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• 2006

The purpose of this raper is to address the negative impedance instability in DC/DC converters. We present the negative impedance instability of PWM DC/DC converters loaded by constant power loads (CPLs). An approach to design digital controllers for DC/DC converters Is presented. The proposed method, called Power Alignment control technique, is applied to DC/DC step-down choppers operating in continuous conduction or discontinuous conduction modes with CPLs. This approach uses two predefined state variables instead of conventional pulse width modulation (PWM) to regulate the output voltage. A comparator compares actual output voltage with the reference and then switches between the appropriate states. It needs few logic gates and comparators to be implemented thus, making it extremely simple and easy to develop using a low-cost application specific integrated circuit (ASIC) for converters with CPLs. Furthermore, stability of the proposed controllers using the small signal analysis as well as the second theorem of Lyapunov is verified. Finally, simulation and analytical results are presented to describe and verify the proposed technique.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2017년도 추계학술대회
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• pp.425-428
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• 2017

본 논문에서는 진동 에너지를 이용하여 에너지를 수확하는 전파 정류 하베스팅 회로를 설계하였다. 설계된 회로는 저전압에서도 전력효율이 우수하도록 Beta-Multiplier를 이용하여 Body-Bias technique을 Negative Voltage Converter에 적용하였으며, Comparator를 Bulk-Driven type으로 설계하였다. 제안된 회로는 $0.35{\mu}m$ CMOS 공정으로 설계하였으며, 설계된 회로의 칩 면적은 $931{\mu}m{\times}785{\mu}m$이다.

• Journal of Electrical Engineering and information Science
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• 제2권3호
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• pp.123-131
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• 1997

Design of single stage AC/DC converter with high power factor for low power level applications is proposed. The proposed converter gives the good power factor correction, low line current harmonic distortions, and tight output voltage regulations. This converter also has a high efficiency by employing an active clamp method and synchronous rectifiers. To verify the performances of the proposed converter, a 90W-converter has been designed. The modelling of this proposed converter is power formed using an averaging technique and based on this model a detailed analysis is carried out. This prototype meets the IEC555-2 requirements satisfactorily with nearly unity power factor and high efficiency.

• 한국전자파학회논문지
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• 제11권8호
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• pp.1407-1413
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• 2000

본 논문에서는 기지국용 전력 증폭기의 혼 변조 성분들을 극도로 억압하기 위해서 Error feedback 방식을 사용한 Feedforward 선형 전력 증폭기를 설계하였다. 특히, 제안된 선형 전력 증폭기는 기존의 피드백 기술의 단점인 증폭 이득의 손실을 없앤 Error feedback 기술과 Feedforward 기술을 혼합하여 적용하였다. 제안된 선형 전력 증폭기는 HP사의 EEsof ADS ver.1.3을 사용해서 설계.제작하였다. 측정결과, 이득 28 ㏈, P1㏈ 31 ㏈m인 주 전력 증폭기에 -7 ㏈m/tone을 갖는 1850 MHz와 1851.25 MHz의 2-tone 신호를 인가한 결과 전체 IMD가 약 35 ㏈ 개선되었다.

• 대한전자공학회논문지TC
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• 제43권12호
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• pp.9-15
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• 2006

본 논문에서는 저전력, 저복잡도 시스템 구현이 가능한 noncoherent IR-UWB (Impulse-radio-based Ultra Wideband: IR-UWB) 무선 통신 시스템을 위한 신호처리부 기술을 제안한다. 제안된 시스템은 OOK(On Off Keying) 변복조 기법을 사용하며, 에너지 검출 기반으로 임펄스 신호를 복원하는 Noncoherent 방식을 사용한다. 특히, 극초단의 펄스 신호를 디지털 신호로 변환하기 위하여 상대적으로 낮은 기준 클럭을 이용하여 나노초 펄스를 검출해 내는 새로운 고속 디지털 샘플러 기술을 제안한다 또한, 데이터 프레임 송수신을 위하여 Turyn 코드를 사용하였으며, 에러 정정을 위하여 길쌈코드를 사용하였고, 수신부에서는 비터비 디코더를 사용하였다 제안된 Noncoherent IR-UWB 시스템의 신호처리부 검증을 위하여, 근거리 고음질의 MP3 데이터 전송 시스템을 설계하였다. 제안된 신호처리부 기술은 FPGA 레벨에서 실제 구현하였으며 각각의 기능 동작을 검증하였다.

• 한국인터넷방송통신학회논문지
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• 제8권4호
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• pp.89-95
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• 2008

해상통신에서 운용되는 OFDM (Orthogonal Frequency Division Multiplexing)통신 단말기는 긴급재난시에도 동작하여야 하므로, 저전력으로 동작하여야 한다. 따라서 Digital Signal Processing (DSP) 동작하는 전압모드 Processor보다 저전력 동작이 가능한 전류모드 FFT (Fast-Fourier-Transform) Processor의 설계가 필요하게 되었다. IVC (Current-to-Voltage Converter)는 전류모드 FFT Processor의 출력 전류를 전압 신호로 바꾸는 디바이스로써, 저전력 OFDM 단말기 동작을 위해 IVC의 전력 손실은 낮아야 하고, FFT의 출력 전류가 전압신호에 대응이 될 수 있도록 넓은 선형적인 동작구간을 가져야 하며, 향후, FFT LSI와 IVC가 한 개의 칩으로 결합되는 것을 고려하면, 작은 크기의 chip size로 설계되어야 한다. 본 논문에서는 선형 동작 구간이 넓은 새로운 IVC를 제안한다. 시뮬레이션 결과, 제안된 IVC는 전류모드 FFT Processor의 출력 범위인 -100 ~100[uA]에서 0.85V~1.4V의 선형동작구간을 갖게 됨을 확인하였다. 제안된 IVC는 전류모드 FFT Processor와 더불어 OFDM을 이용한 저전력 해상 데이터통신 실현을 위한 선도 기술로 유용할 것이다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(5)
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• pp.71-74
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• 2002

We have development the dimming controller using the ac chopper technique. The ac chopper change the amplitude of the input source voltage with the unchanged its frequency. The conventional dimming controller is operated by controlling voltage phase and is consist of the triac. It has a bad characteristic about a current THD and a power factor. But the dimming controller using the at chopper technique has a low current THD and a good power factor. The developed dimming controller is consist of the MOSFET and the low pass filter. The system is operated by the variation circuit of the input source voltage and the microprocessor.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제52권4호
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• pp.177-182
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• 2003

We have proposed the dimming controller using the AC chopper technique. The AC chopper changes the amplitude of the input source voltage with the same frequency. The conventional dimming controller is operated by controlling voltage phase with the triac. It has bad characteristics of the input current THD and the input power factor But the dimming controller using the ac chopper technique has a low current THD and a good power factor. The developed dimming controller is consist of the IGBT and the low pass filter. The system is operated by the variation circuit of the input source voltage and the microprocessor.