• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.223-224
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• 2008

Important element are low cost, high-efficiency crystalline silicon solar cells. in this paper, Will be able to contribute in low cost, high-efficiency silicon solar cells, Applies oxide/nitride passivation, produced screen-printed solar cells. and the Measures efficiency, and evaluated a justice quality oxide/nitride passivation screen-printed solar cells.

• Journal of the Korean Ceramic Society
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• v.38 no.11
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• pp.987-992
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• 2001

A refractory grade low-cost silicon nitride powder was chemically analyzed, purified, and gas pressure sintered with the sintering additives. As-received powder contained a significant amount of free-Si, 0.72 wt% of Fe, 0.5 wt% of al and 0.31 wt% of Ca. Oxygen and carbon contents of the powder were 3.3 wt% and 0.4 wt%, respectively, and it consisted of 96% of $\beta$-phase and 4% of $\alpha$-phase. After lowering the Fe content and nitriding treatment, the powder was sintered with 6 wt% yttria and 2 wt% alumina for 1 h between 1823 K and 2123 K in order to examine the sintering behavior. Fully dense samples were obtained by sintering at 2123k for 2h. For comparison, a commercially available high-grade powder was also sintered at the same time. The low-cost powder showed much slower densification rate than the high-grade powder. Fully dense sample prepared from the low-cost powder contained a number of coarse grains with a low aspect ratio, and its hardness, fracture toughness, flexural strength and thermal shock resistance were not as good as those of the sample prepared with the high-grade powder.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.55 no.12
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• pp.565-569
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• 2006

Plasma enhanced chemical vapor deposition(PECVD) is a well established technique for the deposition of hydrogenated film of silicon nitride (SiNx:H), which is commonly used as an antireflection coating as well as passivating layer in crystalline silicon solar cell. PECVD-SiNx:H films were investigated by varying the deposition and annealing conditions to optimize for the application in silicon solar cells. By varying the gas ratio (ammonia to silane), the silicon nitride films of refractive indices 1.85 - 2.45 were obtained. The film deposited at $450^{\circ}C$ showed the best carrier lifetime through the film deposition rate was not encouraging. The film deposited with the gas ratio of 0.57 showed the best carrier lifetime after annealing at a temperature of $800^{\circ}C$. The single crystalline silicon solar cells fabricated in conventional industrial production line applying the optimized film deposition and annealing conditions on large area substrate of size $125mm{\times}125mm$ (pseudo square) was found to have the conversion efficiencies as high as 17.05 %. Low cost and high efficiency silicon solar cells fabrication sequence has also been explained in this paper.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.280-284
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• 2004

Multicrystalline silicon wafers were textured in an alkaline bath, basically using sodium hydroxide and in acidic bath, using mainly hydrofluoric acid (HF), nitric acid $(HNO_3)$ and de-ionized water (DIW). Some wafers were also acid polished for the comparative study. Comparison of average reflectance of the samples treated with the new recipe of acidic solution showed average diffuse reflectance less than even 5 percent in the optimized condition. Solar cells were thus fabricated with the samples following the main steps such as phosphorus doping for emitter layer formation, silicon nitride deposition for anti-reflection coating by plasma enhanced chemical vapor deposition (PECVD) and front surface passivation, screen printing metallization, co-firing in rapid thermal processing (RTP) Furnace and laser edge isolation and confirmed >14 % conversion efficiency from the best textured samples. This isotropic texturing approach can be instrumental to achieve high efficiency in mass production using relatively low cost silicon wafers as starting material.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.109-109
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• 2010

$Er^{3+}$ ion shows a stable and efficient luminescence at 1.54mm due to its $^4I_{13/2}\;{\rightarrow}\;^4I_{15/2}$ intra-4f transition. As this corresponds to the low-loss window of silica-based optical fibers, Er-based light sources have become a mainstay of the long-distance telecom. In most telecom applications, $Er^{3+}$ ions are excited via resonant optical pumping. However, if nanocluster-Si (nc-Si) are co-doped with $Er^{3+}$, $Er^{3+}$ can be excited via energy transfer from excited electrical carriers in the nc-Si as well. This combines the broad, strong absorption band of nc-Si with narrow, stable emission spectra of $Er^{3+}$ to allow top-pumping with off-resonant, low-cost broadband light sources as well as electrical pumping. A widely used method to achieve nc-Si sensitization of $Er^{3+}$ is high-temperature annealing of Er-doped, non-stoichiometric amorphous thin film with excess Si (e.g.,silicon-rich silicon oxide(SRSO)) to precipitate nc-Si and optically activate $Er^{3+}$ at the same time. Unfortunately, such precipitation and growth of nc-Si into Er-doped oxide matrix can lead to $Er^{3+}$ clustering away from nc-Si at anneal temperatures much lower than ${\sim}1000^{\circ}C$ that is necessary for full optical activation of $Er^{3+}$ in $SiO_2$. Recently, silicon-rich silicon nitride (SRSN) was reported to be a promising alternative to SRSO that can overcome this problem of Er clustering. But as nc-Si formation and optical activation $Er^{3+}$ remain linked in Er-doped SRSN, it is not clear which mechanism is responsible for the observed improvement. In this paper, we report on investigating the effect of separating the nc-Si formation and $Er^{3+}$ activation by using hetero-multilayers that consist of nm-thin SRSO or SRSN sensitizing layers with Er-doped $SiO_2$ or $Si_3N_4$ luminescing layers.

• Tribology and Lubricants
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• v.35 no.5
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• pp.274-285
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• 2019

Chemical mechanical polishing (CMP), which is a material removal process involving chemical surface reactions and mechanical abrasive action, is an essential manufacturing process for obtaining high-quality semiconductor surfaces with ultrahigh precision features. Recent rapid growth in the industries of digital devices and semiconductors has accelerated the demands for processing of various substrate and film materials. In addition, to solve many issues and challenges related to high integration such as micro-defects, non-uniformity, and post-process cleaning, it has become increasingly necessary to approach and understand the processing mechanisms for various substrate materials and abrasive particle behaviors from a tribological point of view. Based on these backgrounds, we review recent CMP R&D trends in this study. We examine experimental and analytical studies with a focus on substrate materials and abrasive particles. For the reduction of micro-scratch generation, understanding the correlation between friction and the generation mechanism by abrasive particle behaviors is critical. Furthermore, the contact stiffness at the wafer-particle (slurry)-pad interface should be carefully considered. Regarding substrate materials, recent research trends and technologies have been introduced that focus on sapphire (${\alpha}$-alumina, $Al_2O_3$), silicon carbide (SiC), and gallium nitride (GaN), which are used for organic light emitting devices. High-speed processing technology that does not generate surface defects should be developed for low-cost production of various substrates. For this purpose, effective methods for reducing and removing surface residues and deformed layers should be explored through tribological approaches. Finally, we present future challenges and issues related to the CMP process from a tribological perspective.

• Proceedings of the IEEK Conference
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• 2002.06a
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• pp.439-442
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• 2002

We present in this Paper a microwave Power sensor fabricated by a standard CMOS process and a bulk micromachining process. The sensor consists of a CPW transmission line, a resistor as a healer, and thermocouple arrays. An input microwave heater, the resistor so that the temperature rises proportionally to the microwave power and tile thermocouple arrays convert it to an electrical signal. The sensor uses air bridged 8round of CPW realized by wire bonding to reduce tile device size and cost and to improve the thermal impedance. Al/poly-Si junctions are used for the thermocouples. Poly-Si is used for tile resister and Aluminium is for transmission line. The resistor and hot junctions of the thermocouples are placed on a low stress silicon nitride diaphragm to minimize a thermal loss. The fabricated device operates properly from 1㎼ to 100㎽\ulcorner of input power. The sensitivity was measured to be ,3.2～4.7 V/W.

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.3
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• pp.214-222
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• 2015

The superiority of gallium nitride FET (GaN FET) over silicon MOSFET is examined in this paper. One of the outstanding features of GaN FET is low reverse-recovery charge, which enables continuous conduction mode operation of totem-pole bridgeless boost power factor correction (PFC) circuit. Among many bridgeless topologies, totem-pole bridgeless shows high efficiency and low conducted electromagnetic interference performance, with low cost and simple control scheme. The operation principle, control scheme, and circuit implementation of the proposed topology are provided. The converter is driven in two-module interleaved topology to operate at a power level of 5.5 kW, whereas phase-shedding control is adopted for light load efficiency improvement. Negative bias circuit is used in gate drivers to avoid the shoot-through induced by high speed switching. The superiority of GaN FET is verified by constructing a 5.5 kW prototype of two-module interleaved totem-pole bridgeless boost PFC converter. The experiment results show the highest efficiency of 98.7% at 1.6 kW load and an efficiency of 97.7% at the rated load.

• Journal of the Korean Society for Precision Engineering
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• v.20 no.5
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• pp.218-224
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• 2003

This paper describes a novel MEMS integration technique on a CMOS chip. MEMS integration on CMOS circuit has many advantages in view of manufacturing cost and reliability. The surface topography of a CMOS chip from a commercial foundry has 0.9 ${\mu}{\textrm}{m}$ bumps due to the conformal coating on aluminum interconnect patterns, which are used for addressing each MEMS element individually. Therefore, it is necessary to achieve a flat mirror-like CMOS chip fer the microelectromechanical system (MEMS) such as micro mirror array. Such CMOS chip needs an additional thickness of the dielectric passivation layer to ease the subsequent planarization process. To overcome a temperature limit from the aluminum thermal degradation, this study uses RF sputtering of silicon nitride at low temperature and then polishes the CMOS chip together with the surrounding dummy pieces to define a polishing plane. Planarization reduces 0.9 ${\mu}{\textrm}{m}$ of the bumps to less than 25 nm.