• IEMEK Journal of Embedded Systems and Applications
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• v.8 no.1
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• pp.25-29
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• 2013

Recently ARM processor's processing power has been increasing rapidly as it has been applied to consumer electronics products. Because of its computing power and low power consumption, it is used to various embedded systems.( including vision processing systems.) Embedded linux that provides well-made platform and GUI is also a powerful tool for ARM based embedded systems. So short period to develop is one of major advantages to the ARM based embedded system. However, for real-time date processing applications such as an image processing system, ARM needs additional equipments such as FPGA that is suitable to parallel processing applications. In this paper, we developed an embedded system using ARM processor and FPGA. FPGA takes time consuming image preprocessing and numerical algorithms needs floating point arithmetic and user interface are implemented using the ARM processor. Overall processing speed of the system is 60 frames/sec of VGA images.

• Korea Multimedia Society
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• v.7 no.4
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• pp.30-39
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• 2003

• IEMEK Journal of Embedded Systems and Applications
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• v.13 no.3
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• pp.133-141
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• 2018

There are increasing interests on smart home systems. However, most of the existing works focus on the functionality itself. In this paper, we propose an extensible smart home system based on low power networking such as CoAP, 6LoWPAN, and Zigbee. The proposed home IoT system consists of Home APP, Home Server, Home Broker, and Power Devices. Each component of the system is connected by the low-power network technologies aforementioned. As the end device, Power Device senses the current consumption of the attached appliance and controls the power to it. Power Device reports the sensing data to Home Server via Home Broker. The Home Broker enhances the scalability of the system. Home Broker extends the service area and the user's services, and it manages the connection of the underlying devices and processes, and transmits data to Home Server from Power Devices. Through the experimental evaluation, we show that the proposed system achieves the design goals such as extensibility and low power networking.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.3
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• pp.207-220
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• 2011

Coarse-grained reconfigurable architecture (CGRA) based embedded systems aims to achieve high system performance with sufficient flexibility to map a variety of applications. However, the CGRA has been considered as prohibitive one due to its significant area/power overhead and performance bottleneck. In this work, I propose reconfigurable multi-array architecture to reduce power/area and enhance performance in configurable embedded systems. The CGRA-based embedded systems that consist of hierarchical configurable computing arrays with varying size and communication speed were examined for multimedia and other applications. Experimental results show that the proposed approach reduces on-chip area by 22%, execution time by up to 72% and reduces power consumption by up to 55% when compared with the conventional CGRA-based architectures.

• The KIPS Transactions:PartD
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• v.18D no.1
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• pp.45-56
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• 2011

The importance of low-power embedded system is being increased. The studies on low-power system have been performed in issues of hardware architecture and operating system. However because the behaviors of software control the working of hardware devices, the power analysis of software is one of critical issues in energy-efficient embedded system development. This paper proposes a technique to extract tasks from software design models with considering power consumption. We first define the criteria for task extraction, and then propose the way to separate out the task from UML 2.0 design models. Our technique can provide the chance to reduce the power consumption as well as to fulfill the performance requirement in the early phase of software development.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.7
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• pp.454-461
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• 2007

Portable embedded systems have recently become smaller in size and offer a variety of junctions for users. These systems require high performance processors to handle the many functions and also a small battery to fit inside the system. However, due to its size, the battery life has become a major issue. It is important to have both efficient power design and management for each function, while optimizing processor voltage and clock frequency in order to extend the battery life of the system. In this paper, we calculated the efficiency of power in optimizing power rail. This system has two microprocessors. One is used to play music and movie files while the other is for DMB. In order to reduce power consumption, the DMB microprocessor is turned of while music or videos are played. Lastly, DVFS is applied to the processor in the system to reduce power consumption. Experimental results of the implemented system have resulted in reduced power consumption.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.264-267
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• 2000

This paper describes a real-time 3D sound localization algorithm to be implemented with the use of a Bow power embedded DSP. This algorithm first divides the audible frequency band into three, on the basis of the analysis of the sound reflection and diffraction effects through different media from a certain sound source to human ears, and then in each subband a specific procedure is devised fur the 3D sound localization so as to operate real-time on a low power embedded DSP This algorithm aims at providing a listener with the 3D sound effects through a headphone at low cost and low power consumption.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.36-43
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• 2008

The OS has the manager of the overall system operation, and has the exact information of the running system. Power management by the OS may have great impact for the optimization of the power consumption. We implement E-ACPI, an extended ACPI which is designed for an advanced power management of embedded systems. In this paper, we address (i) how we extend the exiting ACPI to E-ACPI, (ii) technical challenges to overcome in implementation, and (iii) flow we port our E-ACPI to an embedded linux system in this paper. Experimental results show that our E-ACPI is very useful and effective in practice.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.6B
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• pp.641-647
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• 2009

This paper proposes an improved predictive dynamic power management (DPM) scheme and a task scheduling algorithm to reduce unnecessary power consumption in embedded systems. The proposed algorithm performs pre-scheduling to minimize unnecessary power consumption. The proposed predictive DPM utilizes a scheduling library provided by the system to reduce computation overhead. Experimental results show that the proposed algorithm can reduce power consumption by 22.3% on the average comparing with the LLF algorithm for DPM-enable system scheduling.

• ETRI Journal
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• v.36 no.5
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• pp.808-818
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• 2014

To deal with the major challenges of embedded sensor networks, we consider the use of magnetic fields as a means of reliably transferring both information and power to embedded sensors. We focus on a power allocation strategy for an orthogonal frequency-division multiplexing system to maximize the transferred power under the required information capacity and total available power constraints. First, we consider the case of a co-receiver, where information and power can be extracted from the same signal. In this case, we find an optimal power allocation (OPA) and provide the upper bound of achievable transferred power and capacity pairs. However, the exact calculation of the OPA is computationally complex. Thus, we propose a low-complexity power reallocation algorithm. For practical consideration, we consider the case of a separated receiver (where information and power are transferred separately through different resources) and propose two heuristic power allocation algorithms. Through simulations using the Agilent Advanced Design System and Ansoft High Frequency Structure Simulator, we validate the magnetic-inductive channel characteristic. In addition, we show the performances of the proposed algorithms by providing achievable ${\eta}$-C regions.