• Proceedings of the KIEE Conference
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• 2006.10d
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• pp.173-176
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• 2006

This paper discusses the ZVS/ ZVZCS Three-Level converter using the minimum auxiliary circuit. A primary auxiliary circuit, which consists of one coupled inductor is added in the primary circuit to provide ZVZCS conditions to primary switches. ZVS is for outer switches and ZCS or ZVS is for inner switches. Many advantages including simple circuit topology high efficiency, and low cost make this converter attractive for high power applications. The principle of operation, feature and design considerations arc illustrated and verified through the experiment with a 2kHz 400kHz IGBT based experimental circuit.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.7
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• pp.659-664
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• 2016

In this paper, we suggest operational trans-conductance amplifier(OTA) for current-mode FIR filter that can be used in a digital circuit system requiring high operating frequency and low power consumption. The current-mode signal processing is one of the very innovative design method for a low power consumption system with high operating frequency because it shows a constant power regardless of frequency. From the simulation result using 0.35um CMOS process, when Vdd is 2V, it is confirmed that the proposed circuit showed the dynamic range of the about 1V, about 50% of supply voltage and output current swing of about 0~200uA. Also, the power consumption was evaluated with about 21uW and the active size for an integration was measured with $71um{\times}166um$.

• The Journal of the Korea Contents Association
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• v.7 no.2
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• pp.92-99
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• 2007

This paper presented a low power design of a 32bit block cypher processor reduced from the original 128bit architecture. The primary purpose of this research is to evaluate physical implementation results rather than theoretical aspects. The data path and diffusion function of the processor were reduced to accommodate the smaller hardware size. As a running example demonstrating the design approach, we employed a modified ARIA algorithm having four S-boxes. The proposed 32bit ARIA processor comprises 13,893 gates which is 68.25% smaller than the original 128bit structure. The design was synthesized and verified based on the standard cell library of the MagnaChip's 0.35um CMOS Process. A transistor level power simulation shows that the power consumption of the proposed processor reduced to 61.4mW, which is 9.7% of the original 128bit design. The low power design of the block cypher Processor would be essential for improving security of battery-less wireless sensor networks or RFID.

• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.460-463
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• 1999

A new multi-step voltage source inverter is proposed in this paper. The proposed scheme is composed of the double-connected 12-step inverter with an auxiliary circuit. The auxiliary circuit includes two voltage dividing capacitors, two switching devices and a low KVA autotransformer. The resultant system is shown to be a 24-step inverter suitable for large scale SVC applications in which the PWM method can not be employed. The design parameters are derived from the analysis of voltages and currents by means of switching functions. The simulation results verify the proposed concept.

• Journal of Information Display
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• v.6 no.1
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• pp.17-21
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• 2005

We explored a new way of designing dynamic logic gates with low temperature polysilicon thin film transistors to increase the speed. The proposed architecture of logic gates utilizes the structural advantage of smaller junction capacitance of thin film transistors. This method effectively blocks leakage of current through the thin film transistors. Furthermore, the number of transistors used in logic gates is reduced thereby reducing power consumption and chip area. Through HSPICE .simulation, it is confirmed that the circuit speed is also improved in all logic gates designed.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.24 no.1
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• pp.105-111
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• 2010

This article studies the design of DC-DC Converter to convert low-voltage energy sources generated from renewable power like battery power, photovoltaic power, or fuel cells into high-voltage ones. The circuit topology of H-bridge Converter to convert input voltage, 24[V], into out voltage, 400[V], was realized through applying phase shift angle control so as to manage electric power and voltage in the output side. The advantages of the converter system suggested are the low cost as well as current stress reduction, high efficiency, reliability, and simplified maintenance. It is also found that the system is highly useful to produce residential electric power.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.24-33
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• 2009

The transition of auxiliary lines for transmitting coding information has been one of the major obstacles to restricting the scalability of Sequence Switch Coding (SSC) algorithms. A new design of SSC which does not use auxiliary lines is presented in this paper. The new design makes overhead transitions far less than the previous designs that use auxiliary lines. By applying the new technique, more than 50% of overhead transitions have been reduced, leading to the increase of 30% of the overall efficiency of SSC algorithm.

• Proceedings of the KIEE Conference
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• 2006.04b
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• pp.247-250
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• 2006

This paper presents the single-stage High Power Factor TSFC(Two-Switch Forward Converter). Recently, due to growing concern about the harmonic pollution of power distribution systems and the adoption of standards such as ICE 61000-3-2 and IEEE 519, There is a need to reduce the harmonic contents of AC line currents of power supplies. This research proposed the single-stage two switch forward circuit for low voltage and high current output. The principle of operation, feature and design considerations are illustrated and verified through the experiment with a 200W(5V, 40A) 200kHz MOSFET based experimental circuit.

• Proceedings of the KIEE Conference
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• 2006.10d
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• pp.169-172
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• 2006

This paper presents the single-stage High Power Factor AC/DC Two-Switch Forward Converter (TSFC). Recently, due to growing concern about the harmonic pollution of power distribution systems and the adoption of standards such as ICE 61000-3-2 and IEEE 519, There is a need to reduce the harmonic contents of AC line currents of power supplies. This research proposed the single-stage two switch forward circuit for low voltage and high current output. The principle of operation, feature and design considerations are illustrated and verified through the simulation with a 200W(5V, 40A) 200kHz MOSFET based experimental circuit.

• Proceedings of the KIPE Conference
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• 2001.07a
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• pp.673-676
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• 2001

In this paper, the improved zero-voltage transition(ZVT) PWM boost converter using an inductor feedback technique is proposed. The improved circuit uses a low-voltage zener diode to reduce the turn-off witching loss of the auxiliary witch and EMI noise. Using this technique, soft-witching for the auxiliary switch is guaranted at wide line and load ranges and some of the energy circulating in the auxiliary circuit is fed to the load Since the active switches are turned on and off softly, the witching losses and EMI noise are reduced significantly and the higher efficiency of the system is achieved. In this paper, the modes of converter operation are explained and analyzed, design guidelines are given, and experimental results of 1kW, 100kHz prototype system are presented.