• 한국전자파학회:학술대회논문집
• /
• 한국전자파학회 2002년도 종합학술발표회 논문집 Vol.12 No.1
• /
• pp.16-20
• /
• 2002

This paper describes the resistive FET mixer with low IF for the 4-Ch DBF(Digital Beam Forming) receiver with LNA(Low Noise Amplifier). This DBF receiver based on the direct conversion method is generally suitable for high-speed wireless mobile communications. A radio frequency(RF), a local oscillator(LO) and an intermediate frequency(IF) considered in this research are 2.09 ㎓, 2.08 ㎓ and 10㎒, respectively. The RF input power, LO input power and Vgs are used -10㏈m, 6㏈m and -0.4 V, respectively. In the 4-Ch resistive FET mixer with LNA, the measured IF and harmonic components of 10㎒, 20㎒, 2.09㎓ and 4.17㎓ are about -12.5 ㏈m, -57㏈m, -40㏈m and -54㏈m, respectively. The IF output power observed at each channel of 10㎒ is about -12.5㏈m and it is higher 27.5 ㏈m than the maximum harmonic component of 2.09㎓. Each IF output spectrum of the 4-Ch is observed almost same value and it shows a good agreement with the prediction.

• 한국통신학회논문지
• /
• 제25권5A호
• /
• pp.743-750
• /
• 2000

본 논문에서는, 디지털 IF 다운 샘플러와 업 샘플러의 저전력 구현을 위한 블록 필터링 아키텍처를 제안한다. 소프트웨어 라디오와 같은 차세대 이동통신 방식에서 디지털 IF 다운 샘플러와 업 샘플러의 효율적인 구현방법이 더욱더 요구되어가고 있는 추세이다. 디지털 IF 다운 샘플러는 앞단에 데시메이션 필터를 수반하여 구성되며, 업 샘플러는 뒷단에 인터폴레이션 필터가 수반디어 구성된다. 본 논문의 다운 샘플러 아키텍처에서는 블록 필터링 구조가 갖는 병렬처리 구조를 이용하여 필터를 구현하였으며, 블록 필터링 아키텍처에서 구조적으로 생겨나는 업 샘플링을 직렬로 연결되는 다운 샘플러와 상쇄시킴으로서 효과적인 구조가 만들어짐을 보인다. 또한 업 샘플러 아키텍처에서는 인터폴레이션 필터의 블록 필터링에서 만들어지는 다운 샘플링이 앞단의 업 샘플러와 상쇄되어 병렬처리와 저속의 처리가 가능해짐을 보인다. 본 논문에서 제안된 아키텍처와 Polyphase 아키텍처를 비교 분석한다. 리와 저속의 처리가 가능해짐을 보인다. 본 논문에서 제안된 아키텍처와 Polyphase 아키텍처를 비교 분석한다.

• Journal of electromagnetic engineering and science
• /
• 제2권2호
• /
• pp.117-123
• /
• 2002

This paper describes the design for the resistive FET mixer with low If for the 4-Ch DBF(Digital Beam Forming) receiver This DBF receiver based on the direct conversion method is generally suitable for high-speed wireless mobile communications. A radio frequency(RF), a local oscillator(LO) and an intermediate frequency(If) considered in this research are 2.09 GHz, 2.08 CHz and 10 MHz, respectively. This mixer is composed of band pass filter, a low pass filter and a DC bias circuit. Super low noise HJ FET of NE3210S01 is considered in design. The RE input power, LO input power and Vcs are used -10 dBm, 6 dBm and -0.4 V, respectively. In the 4-Ch resistive FET mixer, the measured If and harmonic components of 10 MHe, 20 MHz and 2.087 CHz are about -19.2 dBm, -66 dBm and -48 dBm, respectively The If output power observed at each channel of 10 MHz is about -19.2 dBm and it is higher 28.8 dBm than the maximum harmonic component of 2.087 CHz. Each If output spectrum of the 4-Ch is observed almost same value and it shows a good agreement with the prediction.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2007년도 심포지엄 논문집 정보 및 제어부문
• /
• pp.252-254
• /
• 2007

In this paper, we will introduce an encoding algorithm of LDPC Codes in Direct-Sequence UWB systems. We evaluate the performance of the coded systems in an AWGN channel. This new algorithm is based on the Jacket matrics. Mathematically let A = ($a_{kl}$) be a matnx, if $A^{-1}$ = $(a^{-1}_{kl})^r$,then the matrix A is a Jacket matrix. If the Jacket matrices if Low density, the inverse matrices is also Low density which is very important to the introduced encoding algorithm.

• Journal of electromagnetic engineering and science
• /
• 제4권4호
• /
• pp.143-149
• /
• 2004

This paper describes characteristics of the single-balanced low IF resistive FET mixer for the digital beam forming(DBF) receiver. This DBF receiver based on the direct conversion method is designed with Low IF I and Q channel. A radio frequency(RF), a local oscillator(LO) and an intermediate frequency(IF) considered in this research are 1950 MHz, 1940 MHz and 10 MHz, respectively. Super low noise HJ FET of NE3210S01 is considered in design. The measured results of the proposed mixer are observed IF output power of -22.8 dBm without spurious signal at 10 MHz, conversion loss of -12.8 dB, isolation characteristics of -20 dB below, 1 dB gain compression point(PldB) of -3.9 dBm, input third order intercept point(IIP3) of 20 dBm, output third order intercept point(OIP3) of 4 dBm and dynamic range of 30 dBm. The proposed mixer has 1.0 dB higher IIP3 than previously published single-balanced resistive and GaAs FET mixers, and has 3.0 dB higher IIP3 and 4.3 dB higher PldB than CMOS mixers. This mixer was fabricated on 0.7874 mm thick microstrip $substrate(\varepsilon_r=2.5)$ and the total size is $123.1\;mm\times107.6\;mm$.

• 한국정보통신학회논문지
• /
• 제8권4호
• /
• pp.879-885
• /
• 2004

본 논문에서는 DDC(Digital Down Convertor)를 가지는 디지털 수신기의 적응 신호처리에 대해 서술하였다. DDC는 NCO(Numerically Controlled Oscillator)와 디지털 LPF(Low Pass Filter)로 구성되어 있으며, 수치적 알고리즘에 의해 수신된 신호를 처리한다. 통과대역 샘플링 기법을 이용한 디지털 수신기의 시뮬레이션 결과를 보여주고 있으며, 수치적으로 처리되는 DDC에 의해 수신된 low IF 신호가 zero IF 신호로 변환되는 것을 확인하였다 또한, 고분해능을 가지는 MUSIC(Multiple Signal Classification) 알고리즘을 이용한 DOA(Direction Of Arrivals) 추정 기법을 기술하고 있다 DOA의 분해능의 정확도가 입력 샘플링 수와 안테나 소자 수에 의존하는 것을 확인하였다

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 B
• /
• pp.894-897
• /
• 2003

Recently, the rapid growth of mobile radio system has led to an increasing demand of low-cost high performance communication IC's. In this paper, we have designed RF front end for wireless LAN receiver employ zero-IF architecture. A low-noise amplifier (LNA) and double-balanced mixer is included in a front end. The zero-IF architecture is easy to integrate and good for low power consumption, so that is coincided to requirement of wireless LAN. But the zero-IF architecture has a serious problem of large offset. Image-reject mixer is a good structure to solve offset problem. Using offset compensation circuit is good structure, too. The front end is implemented in 0.25 ${\mu}m$ CMOS technology. The front end has a noise figure of 5.6 dB, a power consumption of 16 mW and total gain of 22 dB.

• 한방재활의학과학회지
• /
• 제15권1호
• /
• pp.77-87
• /
• 2005

Objectives: This analysis of prescription used for low back pain in the Yomun(腰門) chapter of ${\ll}$Donguibogam(東醫寶鑑); The Precious Mirror of Oriental Medicine${\gg}$ is designed to be helpful to practical use of clinics. Methods : Proscriptions used for low back pain in the Yomun(腰門) chapter of ${\ll}$Donguibogam(東醫寶鑑)${\gg}$ were classified and analyzed according to the frequency of proscriptions and the characteristics of each herbs in proscriptions(efficacy, used frequency, related organs etc.) Results and conclusions : After analysis, we obtained the following results : 1. The causes of low back pain are mainly eohyeol(瘀血), yangheo(陽虛), punghanseub(風寒濕). In care of low back pain, I suppose more efficiency that if Angelica gigas NAKAI(當歸) Cnidium officinale MAKINO(三芎) Prunus persica BATSCH(桃仁) is added when the cause is eohyeol(瘀血), or if Psoralea corylifolia L.(破古紙), Cinnamomum cassia PRESL(肉桂), Foeniculum vulare MILL(茴香), Eucommia ulmoides OLIV.(杜冲), Citrus unshiu MARKOVICH(陳皮) are added when the cause is yangheo(陽虛), or if Phellodendron amurense RUPR.(黃柏), Notopterygium incisum TING(羌活), Atractylodes Japonica KOIDZ.(蒼朮) are added when the cause is punghanseub(風寒濕).

• 미생물학회지
• /
• 제40권1호
• /
• pp.7-11
• /
• 2004

eIF5B는 단백질합성의 개시 인자로서 Met-$tRNA^{Met}$을 AUG 개시코돈에 전달하고, 리보솜의 두 소단위체 결합을 유도한다. 이 인자의 기능을 연구할 목적으로 eIF5B를 코딩하는 FUN12 유전자의 5'말단 부위를 삭제하는 연구를 수행하였다. 프로모터의 대부분을 삭제한 FUN12를 함유한 pRS효모벡터를 FUN12가 삭제되어 천천히 자라는 돌연변이주 ($fun12{\Delta}g$)에 전달하였을 때 그 표현형을 부분적으로 상보하였다. 위와 같이 제조된 벡터에서 N-말단이 상실된 eIF5B 단백질이 발현되었고, 그 양이 정상 균주에서 발현되는 eIF5B 양의 약 5%에 불과하였다. 이와 같이 부분적으로 성장을 상보한 균주에서 발현된 적은 양의 단백질합성개시 인자 eIF5B는 직접적으로 그 성장을 제한하는 요소로 작용한다. 이러한 균주에서 성장의 제한인자인 eIF5B는 in vitro 에서도 역시 전체 단백질 합성의 활성을 조절하였다.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제5권4호
• /
• pp.276-281
• /
• 2005

This paper presents a low voltage operating IF QPSK receiver block which is consisted of programmable gain amplifier (PGA) and analog to digital converter. This PGA has 6 bit control and 250MHz bandwidth, $0{\sim}20\;dB$ gain range. Using the proposed PGA architecture (low distortion gain control switch block), we can process the continuous fully differential $0.2{\sim}2.5Vpp$ input/output range and 44MHz carrier with 2 MHz bandwidth signal at 1.8V supply voltage. Using the sub-sampling technique (input freq. is $44{\sim}46MHz$, sampling freq. is 25MHz), we can process the IF QPSK signal ($44{\sim}46MHz$) which is the output of the 6 bit PGA. We can get the SNDR 35dB, which is the result of PGA and ADC at full gain mode. We fabricated the PGA and ADC and the digital signal processing block of the IF QPSK with the 0.18um CMOS MIM process 1.8V Supply.