• International journal of advanced smart convergence
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• 제8권4호
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• pp.188-193
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• 2019

This paper is about environment-based low-code and no-code execution platform and execution method that combines hybrid and native apps. In detail, this paper describes the Low-Code/No-Code execution structure that combines the advantages of hybrid and native apps. It supports the iPhone and Android phones simultaneously, supports various templates, and avoids developer-oriented development methods based on the production process of coding-free apps and the produced apps play the role of Java virtual machine (VM). The Low-Code /No-Code (LCNC) development platform is a visual integrated development environment that allows non-technical developers to drag and drop application components to develop mobile or web applications. It provides the functions to manage dependencies that are packaged into small modules such as widgets and dynamically loads when needed, to apply model-view-controller (MVC) pattern, and to handle document object model (DOM). In the Low-Code/No-Code system, the widget calls the AppOS API provided by the UCMS platform to deliver the necessary requests to AppOS. The AppOS API provides authentication/authorization, online to offline (O2O), commerce, messaging, social publishing, and vision. It includes providing the functionality of vision.

• 한국통신학회논문지
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• 제35권7C호
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• pp.587-593
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• 2010

본 논문에서는 extrinsic information transfer (EXIT) chart를 이용하여 다중 안테나 시스템에서 irregular low-density parity-check (LDPC) code를 설계하는 방법을 기술한다. 다중 안테나 기반의 Irregular LDPC code 설계를 위하여 maximum a posteriori probability (MAP) 방식의 다중 안테나 검출 방식이 사용되었으며 수신기는 다중 안테나 검출기와 LDPC 복호기 사이에서 복호된 soft 정보를 주고 받는 turbo iterative 구조를 가정하였다. 다중 안테나 기반의 irregular LDPC code의 edge degree 분포는 EXIT chart와 linear optimization programming 기법을 사용하여 얻을 수 있으며 컴퓨터 시뮬레이션을 통하여 제안된 방법으로 설계된 irregular LDPC code의 성능을 다양한 환경에서 검증하였다.

• 한국통신학회논문지
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• 제32권3C호
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• pp.205-215
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• 2007

This paper presents low latency and/or computation algorithms of iterative codes of turbo codes, turbo product codes and low density parity check codes for use in wireless broadband communication systems. Due to high coding complexity of iterative codes, this paper focus on lower complexity and/or latency algorithms that are easily implementable in hardware and further accelerate the decoding speed.

• 한국지능시스템학회논문지
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• 제19권2호
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• pp.180-184
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• 2009

저전력 환경에서의 메모리 집적도가 증가함에 따라 메모리는 soft error에 매우 민감해졌다. 오류 정정 코드는 일반적으로 양산 이후 메모리의 soft error를 수정하기 위해서 사용된다. 본 논문에서는 새로운 저전력 오류 정정 코드의 설계방법을 제안한다. 오류 정정 코드의 전력소비는 parity check 행렬의 선택을 통해 최소화 될 수 있다. 따라서 오류 정정 코드의 설계는 비선형 최적화 문제로 포함되는데 우리는 다양한 유전 연산자를 포함하는 유전자 알고리즘을 이용하여 이 문제를 해결한다. 제안하는 방법을 Hamming code와 Hsiao code에 적용하여 그 효율성을 입증하였다.

• 한국정보전자통신기술학회논문지
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• 제11권4호
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• pp.430-435
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• 2018

본 논문에서는 부호 길이가 작은 LCPC 부호에 대한 개선된 복호 방식을 제안하였다. LCPC 부호는 터보 부호나 LDPC 부호에 비해 복잡도가 낮고 요구되는 메모리도 적어 IoT 단말 간 통신에 적합하다. IoT 단말은 에너지가 제한되어 있어서 복잡도가 낮아야 하며 종단 간 지연 시간이 짧아야 하는 경우가 많다. 또한, 전송되는 패킷 길이가 작고 IoT 단말의 신호 처리 능력이 작기 때문에 LCPC 부호 시스템이 가능한 한 간단해야 한다. LCPC 부호는 단일 오류는 모두 정정할 수 있고 2개의 오류 중 일부를 정정할 수 있다. 본 논문에서는 변조기 출력단의 소프트 값을 이용하여 2개의 오류를 모두 정정함으로서 복잡도를 증가시키지 않고서도 비트 오율 성능을 개선하였다. 본 논문에서 제안한 복호 방식을 이용하여 시뮬레이션을 한 결과 기존의 복호 방식에 비해 $10^{-4}$의 비트 오율에서 약 1.1[dB]의 부호 이득을 얻을 수 있었다.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2008년도 춘계종합학술대회 A
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• pp.689-692
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• 2008

Hierarchical modulation has been considered for achieving higher data rates in Terrestrial-DMB(T-DMB) systems. And for achieving a higher data rates transmission, the low-priority (LP) data, which is used to carry additional data, such as video data, audio data and textual data, should be perfectly decoded in a certain value of $E_b/N_o$. Unfortunately, the man-made noise badly affects the high-priority (HP) symbol, which is used to carry the conventional data in the existed T-DMB system; and since the advanced T-DMB system is proposed to fit for the legacy T-DMB receivers, the low-priority symbols in the hierarchical modulation are much worse affected by the neighbors, who are both in the same quadrant. Because of the feature that mentioned previously, the turbo code has been considered to deal with the LP data. And due to the degradation which caused by the shortened symbol distance, the error performance of LP data is not sufficient by only using the turbo code. In this paper, we propose a Reed-Solomon code used outside of turbo code, and with the turbo code, it becomes a concatenated code. In this paper, there are some simulation results, within the comparison of those performances, we can see how a Reed-Solomon code is utilized for degradation of error performance which is caused by the hierarchical constellation, and how to design a Reed-Solomon code which is suitable for improving the degradation of error performance.

• Journal of Information Processing Systems
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• 제17권1호
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• pp.191-202
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• 2021

In an Internet of Things (IoT)-configured system, each device executes on-chip software. Recent IoT devices require fast execution time of complex services, such as analyzing a large amount of data, while maintaining low-power computation. As service complexity increases, the service requires high-performance computing and more space for embedded space. However, the low performance of IoT edge devices and their small memory size can hinder the complex and diverse operations of IoT services. In this paper, we propose a remote on-demand software code execution unit using the cloudification of on-chip code memory to accelerate the program execution of an IoT edge device with a low-performance processor. We propose a simulation approach to distribute remote code executed on the server side and on the edge side according to the program's computational and communicational needs. Our on-demand remote code execution unit simulation platform, which includes an instruction set simulator based on 16-bit ARM Thumb instruction set architecture, successfully emulates the architectural behavior of on-chip flash memory, enabling embedded devices to accelerate and execute software using remote execution code in the IoT environment.

• ETRI Journal
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• 제46권3호
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• pp.485-500
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• 2024

A hardware architecture is presented to decode (N, K) polar codes based on a low-density parity-check code-like decoding method. By applying suitable pruning techniques to the dense graph of the polar code, the decoder architectures are optimized using fewer check nodes (CN) and variable nodes (VN). Pipelining is introduced in the CN and VN architectures, reducing the critical path delay. Latency is reduced further by a fully parallelized, single-stage architecture compared with the log N stages in the conventional belief propagation (BP) decoder. The designed decoder for short-to-intermediate code lengths was implemented using the Virtex-7 field-programmable gate array (FPGA). It achieved a throughput of 2.44 Gbps, which is four times and 1.4 times higher than those of the fast-simplified successive cancellation and combinational decoders, respectively. The proposed decoder for the (1024, 512) polar code yielded a negligible bit error rate of 10^-4 at 2.7 E_b/N_o (dB). It converged faster than the BP decoding scheme on a dense parity-check matrix. Moreover, the proposed decoder is also implemented using the Xilinx ultra-scale FPGA and verified with the fifth generation new radio physical downlink control channel specification. The superior error-correcting performance and better hardware efficiency makes our decoder a suitable alternative to the successive cancellation list decoders used in 5G wireless communication.

• 대한전자공학회논문지
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• 제20권5호
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• pp.23-30
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• 1983

Duobinary 선로부호를 수정하여 "0"의 길이가 제한된 최소 대역폭 선로부호를 설계하였다. 이 새로운 부호는 duobinary와는 달리 "0"기 길이가 제한되어 self-clocking 특성을 가지므로, 수신측의 원활한 동기 재생을 위한 송신측의 데이타 스크램블링이 필요없다. 또한, 눈폭(eye width)과 오판율(error rate) 특성도 duobinary에 버금하며, 전력스펙트럼도 그에 유사하여, optical fiber와 같은 저역통파특성의 선로에 적합하다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.999-1000
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• 2006

The LDPC Code is focusing a powerful FEC(Forward Error Correction) codes for 4G Mobile Communication system. LDPC codes are used minimizing channel errors by modeling AWGN Channel as VDSL system. The performance of LDPC code is better than that of turbo code in long code word on iterative decoding algorithm. LDPC code are encoded by sparse parity check matrix. there are decoding algorithms for a LDPC code, Bit Flipping, Message passing, Sum-Product. Because LDPC Codes use low density parity bit, mathematical complexity is low and relating processing time becomes shorten.