• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.3A
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• pp.345-355
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• 2006

The RF Module which can be adjusted for a digital terrestrial and multi standard(DVB-C, ISDB-T, DVB-H) reception is developed. The Module by single conversion does divide a broadband($45MHz{\sim}860MHz$) broadcasting channels into three-bands(UHF, VHF_HIGH, VHF_LOW) to satisfy some electrical performances such as image signal rejection, phase noise, IF flatness etc and digital reception specifications such as analog and digital adjacent channel protection, co-channel protection which is important in environment with co-existence both analog and digital broadcasting systems.

• Journal of information and communication convergence engineering
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• v.13 no.2
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• pp.139-143
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• 2015

A push-push voltage controlled dielectric resonator oscillator (VCDRO) with a modified frequency tuning structure using broadside couplers is investigated. The push-push VCDRO designed at 16 GHz is manufactured using a low temperature co-fired ceramic (LTCC) technology to reduce the circuit size. The frequency tuning structure using a broadside coupler is embedded in a layer of the A6 substrate by using the LTCC process. Experimental results show that the fundamental and third harmonics are suppressed above 15 dBc and 30 dBc, respectively, and the phase noise of push-push VCDRO is -97.5 dBc/Hz at an offset frequency of 100 kHz from the carrier. The proposed frequency tuning structure has a tuning range of 4.46 MHz over a control voltage of 1-11 V. This push-push VCDRO has a miniature size of 15 mm×15 mm. The proposed design and fabrication techniques for a push-push oscillator seem to be applicable in many space and commercial VCDRO products.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.5
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• pp.1035-1039
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• 2012

In this paper, we developed a 94 GHz waveguide VCO(voltage controlled oscillator) using a GaAs-based Gunn diode and a varactor diode. The cavity is designed for fundamental mode at 47 GHz and operated at second harmonic of 94 GHz. Bias posts for diodes operate as LPF(low pass filter) and resonator. The fabricated waveguide VCO achieves an oscillation bandwidth of 760 MHz. Output power is from 12.61 to 15.26 dBm and phase noise is -101.13 dBc/Hz at 1 MHz offset frequency from the carrier.

• Journal of Information Processing Systems
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• v.15 no.3
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• pp.604-615
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• 2019

Single-user spectrum sensing is susceptible to multipath effects, shadow effects, hidden terminals and other unfavorable factors, leading to misjudgment of perceived results. In order to increase the detection accuracy and reduce spectrum sensing cost, we propose an adaptive cooperative sensing strategy based on an estimated signal-to-noise ratio (SNR). Which can adaptive select different sensing strategy during the local sensing phase. When the estimated SNR is higher than the selection threshold, adaptive double threshold energy detector (ED) is implemented, otherwise cyclostationary feature detector is performed. Due to the fact that only a better sensing strategy is implemented in a period, the detection accuracy is improved under the condition of low SNR with low complexity. The local sensing node transmits the perceived results through the control channel to the fusion center (FC), and uses voting rule to make the hard decision. Thus the transmission bandwidth is effectively saved. Simulation results show that the proposed scheme can effectively improve the system detection probability, shorten the average sensing time, and has better robustness without largely increasing the costs of sensing system.

• ETRI Journal
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• v.46 no.2
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• pp.323-332
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• 2024

Receiver and transmitter monolithic microwave integrated circuit (MMIC) multifunction chips (MFCs) for active phased-array antennas for Ka-band satellite communication (SATCOM) terminals have been designed and fabricated using a 0.15-㎛ GaAs pseudomorphic high-electron mobility transistor (pHEMT) process. The MFCs consist of four-channel radio frequency (RF) paths and a 4:1 combiner. Each channel provides several functions such as signal amplification, 6-bit phase shifting, and 5-bit attenuation with a 44-bit serial-to-parallel converter (SPC). RF pads are implemented on the bottom side of the chip to remove the parasitic inductance induced by wire bonding. The area of the fabricated chips is 5.2 mm × 4.2 mm. The receiver chip exhibits a gain of 18 dB and a noise figure of 2.0 dB over a frequency range from 17 GHz to 21 GHz with a low direct current (DC) power of 0.36 W. The transmitter chip provides a gain of 20 dB and a 1-dB gain compression point (P1dB) of 18.4 dBm over a frequency range from 28 GHz to 31 GHz with a low DC power of 0.85 W. The P1dB can be increased to 20.6 dBm at a higher bias of +4.5 V.

• The Transactions of the Korean Institute of Power Electronics
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• v.4 no.5
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• pp.462-473
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• 1999

This paper addresses the current measurement issue of all digital field oriented control of ac motors. The p paper focuses on the effect of low-pass filter and also on the sampling of the fundamental component of the m motor current. The low-pass filter, which suppresses the switching noise of the motor current, introduces v variable phase delay according to the current ripple frequency. It is shown that the current sampling error c consists of the fundamental component and high frL'quency ripple components. In this paper, the dependency of t this current sampling e$\pi$or on the reference voltage vector is investigated analytically and a sampling technique i is proposed to minimize the error. The work is based on the three phase symmetry pulse width modulation l inverter driving an induction machine. With this technique, the bandwidth of current regulator can be extended t to the limit given by the switching frequency of the inverter and more precise torque regulation is possible.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.8
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• pp.717-724
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• 2016

This paper presents design of a 40 GHz CMOS PLL frequency synthesizer for a 60 GHz sliding-IF RF transceiver. For stable locking over a wide bandwith for a injection-locked frequency divider, an inductive-peaking technique is employed so that it ensures the PLL can safely lock across the very wide tuning range of the VCO. Also, Injection-locked type LC-buffer with low-phase noise and low-power consumption is added in between the VCO and ILFD so that it can block any undesirable interaction and performance degradation between VCO and ILFD. The PLL is designed in 65 nm CMOS precess. It covers from 37.9 to 45.3 GHz of the output frequency. and its power consumption is 74 mA from 1.2 V power supply.

• Journal of Advanced Marine Engineering and Technology
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• v.17 no.5
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• pp.71-85
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• 1993

The Cycloconverter that the author is going to treat in this paper, has strong advantages over the D.C. Link Inverter in points of chattering torque problem and natural commutation. Thus, the Cycloconverter is expected to be well applied to large and low-speed machines which require better speed control at low frequency. But the control circuit of Cycloconverter has two weak points described as follows. 1) Because of its rather complicated control circuit, it is likely to be illoperating due to unexpected noise signals, thus the higher the accuracy and reliability of the circuit is required to be, the more the circuit may cost. 2) Because the load current is not purely sinusoidal, the Cycloconverter may possibly be destroyed in case of inaccurate convert switching resulted from the difficulties in detecting the load current-zero and the current direction at the moment. In this paper, the author first of all intends to design and build a modified VVVF-type Noncirculating Current Cycloconverter to which recently proposed control methods are applied for improving the circuit simplicity, the control performance, and the system reliability. And then, experiments for observing the output waveforms of the Cycloconverter which is controlled by Singled-Board Computer using 8086 16-bit microprocesser are carried out. Finally the author concludes the result of this study as follows. 1) By replacing the conventional analog control circuits such as Reference Wave Generator, Cosine Timing Wave Generator, and Comparator with softwares, a great circuit simplicity is achieved. 2) The output of the designed Cycloconverter changes its frequency very fast without showing discontinuity of its waveform, and this waveform characteristics enables the smooth speed control of Induction Motor. 3) The design control circuit of Cycloconverter can be applied to the systems of 12 or 24 pulses because of its short processing period.

• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.445-448
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• 2005

A new high efficiency phase shifted full bridge (PSFB) converter for sustaining power module of plasma display panel (PDP) is proposed in this paper .The proposed converter employs the rectifier of voltage doubler type without output inductor. Since it has no output inductor, the voltage stresses of the secondary rectifier diodes can be clamped at the level of the output voltage. Therefore, no dissipative resistor-capacitor (RC) snubber for rectifier diodes is needed and a high efficiency as well as low noise cutout voltage can be realized. In addition, due to elimination of the large output inductor, it features a simple structure, lower cost, less mass, and lighter weight. Furthermore, the proposed converter has wide zero voltage switching (ZVS ) ranges with low current stresses of the primary switches. Also the resonance between the leakage inductor of the transformer and the capacitor of the voltage doubler cell makes the current stresses of the primary switches and rectifier diodes reduced. In this paper, the operational principles, analysis of the proposed converter, and the experimental results are presented.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.3
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• pp.81-87
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• 2016

This paper analysis the AM-SCS-MMA (Adaptive Modulus-Soft Constraint Satisfaction-MMA) based on the adaptive modulus and minimus-disturbance technique in order to improve the stability and robustness in low signal to noise power of current MMA adaptive equalization algorithm. In AM-SCS-MMA, it updates the filter coefficient applying the adaptive modulus and minimum-disturbance technique of deterministic optimization problem instead of LMS or gradient descend algorithm for obtain the minimize the cost function of adaptive equalization. It is possible to improve the equalizer filter stability, robustness to the various noise characteristic and simultaneous reducing the intersymbol interference due to the amplitude and phase distortion occurred at channel. The computer simulation were performed for confirming the improved performance of SCS-MMA. For these, the output signal constellation of equalizer, residual isi, MSE, EMSE (Excess MSE) which means the channel traking capability and SER which means the robustness were applied. As a result of computer simulation, the AM-SCS-MMA have slow convergence time and less residual quantities after steady state, more good robustness in the poor signal to noise ratio, but poor in channel tracking capabilities was confirmed than MMA.