• 산업기술연구
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• 제37권1호
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• pp.32-36
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• 2017

In this study, as part of a research on the development of economical high-performance concrete with high strength and high quality, the physical properties of high-performance concrete were analyzed by substituting a certain amount of low-cost domestic silica fume exempted from the re-importation type distribution structure of the domestic production and the existing high-priced silica fume distribution structure. Performing tests to identify the physical properties of the fresh and hardened concrete and durability analogy of the concrete which use low-cost domestic silica fume and imported silica fume, the chloride ion penetration resistance test result showed that the strength difference between the low-cost silica fume and the imported silica fume is not big but the strength of the low-cost silica fume was measured higher than the imported silica fume. The chloride ion penetration resistance of all variables was measured as "very low". Since the low-cost domestic silica fume can be used as a high-performance admixture of concrete, the results suggest that it is possible to produce a more economical high-performance concrete.

• 한국산업융합학회 논문집
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• 제25권3호
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• pp.379-386
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• 2022

The goal of this research is to verify a performance test system for a low speed, high torque, and harsh reducer at low cost. The reducer rotates a cooling fan with a diameter of 10 meters, in a high temperature (50℃) cooling tower in a geothermal power plant. It requires about 500 kgf·m torque and 47.75 kW power to rotate the fan at a maximum power condition. An expensive dynamometer is commonly used for performance test of a motor or a reducer. In this paper, a low cost system is developed using a hydraulic pump as a load unit to generate torque instead of a dynamometer. We accurately calculated the required power, the flow meter, and the pressure of the pump, and selected to design and optimize the system at minimal cost. The system also applied another reverse reducer and a gearbox to increase the rotational speed and to reduce the torque from the low speed and high torque target reducer. This allows low-cost systems to be built using inexpensive components. The developed system was able to successfully measure the high torque and the low rotational speed of the target reducer at high temperature.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2007년도 하계학술대회 논문집
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• pp.226-228
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• 2007

SRM drive systems are designed to meet operating standards such as low cost, constant torque independent of rotor position, a desired operating speed range, high efficiency, and high performance. In applications using small motors, low cost and high performance with self-starting capabilities are highly desired. This paper discusses a novel two phase SRM (TPSRM) that has high performance characteristics with self-starting capability, low manufacturing cost with a two phase inverter and simple magnetic structure, and high efficiency. The principle of operation, analysis, and simulation for design are presented. The machine design is verified using finite element analysis (FEA) software. Analysis and simulation results are given to validate the TPSRM design.

• 한국산업융합학회 논문집
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• 제24권1호
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• pp.69-77
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• 2021

The widely used low-cost design methodology for IoT devices is very popular. In such a networked device, memory is composed of flash memory, SRAM, DRAM, etc., and because it processes a large amount of data, memory design is an important factor for system performance. Therefore, each device selects optimized design factors such as function, performance and cost according to market demand. The design of a memory architecture available for low-cost IoT devices is very limited with the configuration of SRAM, flash memory, and DRAM. In order to process as much data as possible in the same space, an architecture that supports parallel processing units is usually provided. Such parallel architecture is a design method that provides high performance at low cost. However, it needs precise software techniques for instruction and data mapping on the parallel architecture. This paper proposes an instruction/data mapping method to support optimized parallel processing performance. The proposed method optimizes system performance by actively using hardware and software parallelism.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 컴퓨터소사이어티 추계학술대회논문집
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• pp.45-48
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• 2003

We can easily buy network system for high performance micro-processor, progress computer architecture is caused of high bandwidth and low delay time. Coupling PC-based commodity technology with distributed computing methodologies provides an important advance in the development of single-user dedicated systems. Lately Network is joined PC or workstation by computers of high performance and low cost. Than it make intensive that Cluster system is resembled supercomputer. Unix, Linux, BSD, NT(Windows series) can use Cluster system OS(operating system). I'm chosen linux gain low cost, high performance and open technical documentation. This paper is benchmark performance of Beowulf clustering by UltraSPARC-1K(64bit-RISC processor). Benchmark tools use MPI(Message Passing Interface) and NetPIPE. Beowulf is a class of experimental parallel workstations developed to evaluate and characterize the design space of this new operating point in price-performance.

• 전자공학회논문지A
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• 제31A권6호
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• pp.177-187
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• 1994

In the design of modern computer systems, the speed gap between the CPUs and DRAMs has been a major concern. To relieve this problem at a low cost, several new DRAM architectures have been proposed. This study is aimed at evaluating quantitatively the impact of the new DRAM architectures (synchronous DRAM. dual-RAS synchronous DRAM, and enhanced DRAM) on the memory system performance. We developed a cache and memory simulator and performed various experiments using the traces generated from four benchmark programs. The simulation results show that the new DRAM architectures offer a better performance than a conventional one by 5~30% in a low cost system and their improvement in a high performance system is less than 1%. However, for resonable multiprogramming workoads, additional performance improvement of about 10~28% is expected in a high performance system while 1~3% in a low cost system.

• Journal of Electrical Engineering and Technology
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• 제10권3호
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• pp.1015-1024
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• 2015

This paper introduces a low cost, high efficiency, high performance three-phase unified power quality conditioner (UPQC) by using four-switch three-phase inverters (FSTPIs) and an extra capacitor in the shunt active power filter (APF) side of the UPQC. In the proposed UPQC, both shunt and series APFs are developed by using FSTPIs so that the number of switching devices is reduced from twelve to eight devices. In addition, by inserting an additional capacitor in series with the shunt APF, the DC-link voltage in the proposed UPQC can also be greatly reduced. As a result, the system cost and power loss of the proposed UPQC is significantly minimized thanks to the use of a smaller number of power switches with a lower rating voltage without degrading the compensation performance of the UPQC. Design of passive components for the proposed UPQC to achieve a good performance is presented in detail. In addition, comparisons on power loss, overall system efficiency, compensation performance between the proposed UPQC and the traditional one are also determined in this paper. Simulation and experimental studies are performed to verify the validity of the proposed topology.

• Journal of Power Electronics
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• 제15권3호
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• pp.695-701
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• 2015

Uninterruptible Power Supplies (UPSs) can be largely divided into the passive-standby, line-interactive and double-conversion methods. This paper proposes a double-conversion UPS with a low cost and high performance. This single phase UPS uses a single-loop robust voltage controller and 1-switch voltage doubler strategy PFC. The proposed UPS is composed of a single phase PFC, a half-bridge inverter, a battery charger and a battery discharger. Finally, the validity of proposed UPS was verified by various experimental tests.

• 동아시아식생활학회지
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• 제20권5호
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• pp.823-835
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• 2010

The research aimed to measure the efficiency of using multi stores in a foodservice company using by DEA (data envelopment analysis) which is a new management science technique. The study also attempted to identify relevant variables affecting DEA efficiency in order to suggest methods for improving efficiency. The data were collected from 148 contract foodservice operations, which were operated in similar fashion in October 2009. The DEA efficiency was calculated as an output-oriented BCC Model. Sales, and CSI (customer satisfaction index) were used as output variables whereas food cost, labor cost, and management expense were used as input variables to calculate the DEA efficiency. Operation process variables of the unit consisted of the were consist of ratio of regular employee, ratio of housekeeper, meal counts, meal price, food cost per meal, contract period, number of menu items, forecasting accuracy, order accuracy, inventory turnover, use of processed food, deviation of food cost, number of new menus, and number of events. According to the BCC score and profitability, units were classified into four groups: High efficiency-high profitability (HEHP), High efficiency-low profitability (HELP), Low efficiency-high profitability (LEHP), and Low efficiency-low profitability (LELP). The HEHP group contained 54 units, which mostly contracted management fee type and had a high meal price. The units were also very large and, served three meals. Twenty of the units were operated with high labor cost: most of these were factories and hospitals. The LEHP group contained 20 units, that were mainly office stores of large scale and medium price. Fifty-four LELP group had a low meal price. A high performance group must have high efficiency, profitability, and satisfaction. The BCC score was over 0.969, the meal price was over 4,116 won, the food cost was over 2,077 won, and meal counts per month were over 10,212 meals.

• 전자공학회지
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• 제37권8호
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• pp.50-59
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• 2010

$0.18-{\mu}m$ high voltage technology 13.5V high voltage well-based symmetric EDMOS isolated by MTI was designed and fabricated. Using calibrated process and device model parameters, the characteristics of the symmetric and asymmetric EDMOS have been simulated. The asymmetric EDMOS has higher performance, better $R_{sp}$ / BVDSS figure-of-merit, short-channel immunity and smaller pitch size than the symmetric EDMOS. The asymmetric EDMOST is a good candidate for low-power and smaller source driver chips. The low voltage logic well-based EDMOS process has advantages over high voltage well-based EDMOS in process cost by eliminating the process steps of high-voltage well/drift implant, high-temperature long-time thermal steps, etc. The specific on-resistance of our well-designed logic well-based EDMOSTs is compatible with the smallest one published. TCAD simulation and measurement results show that the improved logic well-based nEDMOS has better electrical characteristics than those of the conventional one. The improved EDMOS proposed in this paper is an excellent candidate to be integrated with low voltage logic devices for high-performance low-power low-cost chips.