• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.7
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• pp.10-16
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• 1999

This paper describes a low voltage swing bus driver using FCSR(Feedback Control Swing voltage Reduction) which can control bus swing voltage within a few hundred of mV. It is proposed to reduce power consumption in On-chip interface, especially for MDL(Merged DRAM Logic) architecture wihich has wide and large capacitance bus. FCSR operates on differential signal dual-line bus and on precharged bus with block controlling fuction. We modeled driver and bus to scale driver size automatically when bus environment is variant. We also modeled coupling capacitance noise(crosstalk) of neighborhood lines which operate on odd mode with parallel current source to analysis crosstalk effect in the victim-line according as voltage transition in the aggressor-line and environment in the victim-line. We built a test chip which was designed to swing 600mV in bus, shows 70Mhz operation at 3.3V, using Hyundai 0.8um CMOS technology. FCSR operate with 250Mhz at 3.3V by Hspice simulation.

• Proceedings of the KIPE Conference
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• 2014.11a
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• pp.66-67
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• 2014

Stabilization of the DC bus voltage is an important task in DC-AC microgrid system with renewable energy source such as solar system. A battery energy storage system (BESS) has become a general solution to stabilize the DC-bus voltage in DC-AC microgrid. This paper develops the analog BESS controller which requires neither computation nor dc-bus voltage measurement, so that the system can be implemented simply and easily. Even though others methods can stabilize and control the DC-bus voltage, it has complicated structure in control and low adaptive capability. The proposed topology is simple but is able to compensate the solar source variation and stabilize the DC-bus voltage under any loads and distributed generation (DG) conditions. In addition, the design of analog controller is presented to obtain a robust system. In order to verify the effectiveness of the proposed control strategy, simulation is carried out by using PSIM software.

• Journal of Power Electronics
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• v.15 no.3
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• pp.806-818
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• 2015

Based on the inherent relationship between dc-bus voltage and grid feeding active power, two dc-bus voltage regulators with different references are adopted for a grid-connected PV inverter operating in both normal grid voltage mode and low grid voltage mode. In the proposed scheme, an additional dc-bus voltage regulator paralleled with maximum power point tracking controller is used to guarantee the reliability of the low voltage ride-through (LVRT) of the inverter. Unlike conventional LVRT strategies, the proposed strategy does not require detecting grid voltage sag fault in terms of realizing LVRT. Moreover, the developed method does not have switching operations. The proposed technique can also enhance the stability of a power system in case of varying environmental conditions during a low grid voltage period. The operation principle of the presented LVRT control strategy is presented in detail, together with the design guidelines for the key parameters. Finally, a 3 kW prototype is built to validate the feasibility of the proposed LVRT strategy.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.2
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• pp.56-62
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• 2002

A new high speed and low voltage swing on-chip BUS using threshold voltage swing driver and dual sense amplifier receiver is proposed. The threshold voltage swing driver reduces the rising time in the bus to 30% of the full CMOS inverter driver and the dual sense amplifier receiver increases twice the throughput. of the conventional reduced-swing buses using sense amplifier receiver. With threshold voltage swing driver and dual sense amplifier receiver combined, approximately 60% speed improvement and 75% power reduction are achieved in the proposed scheme compared to the conventional full CMOS inverter for the on-chip bus.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.12
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• pp.2633-2640
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• 2009

We design a small-area, low-power, and high-speed EEPROM for touch screen controller IC. As a small-area EEPROM design, a SSTC (side-wall selective transistor) cell is proposed, and high-voltage switching circuits repeated in the EEPROM core circuit are optimized. A digital data-bus sensing amplifier circuit is proposed as a low-power technology. For high speed, the distributed data-bus scheme is applied, and the driving voltage for both the EEPROM cell and the high-voltage switching circuits uses VDDP (=3.3V) which is higher than the logic voltage, VDD (=1.8V), using a dual power supply. The layout size of the designed 128-KBit EEPROMIP is $662.31{\mu}m{\times}1314.89{\mu}m$.

• Proceedings of the KIEE Conference
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• 2001.05a
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• pp.74-76
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• 2001

When a Bus voltage is low, the Load-Flour is generally blown up. If Bus voltage is normalized. the convergence of Load-flow is improved. This paper introduces virtual bus with tap. In that case, the Bus admittance will be considered. And the convergence of Load-Flow in applying virtual bus is debated.

• Proceedings of the KIEE Conference
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• 2001.05a
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• pp.7-9
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• 2001

Many developing countries has been voltage unstable and the inter- change capability in Korea is limited by voltage instability. In analyzing voltage stability, load model has been considered as constant power, but actual loads vary as voltage changes. In order to incorporating voltage-dependent load model. we need the low-side of P-V curve that can not be obtained by general load flow algorithm. This paper proposes a modified GCF algorithm to obtain a full low-side of P-V curve and a accurate voltage assessment index considering load model. 5-bus sample system and 19-bus real power system are applied to simulate the proposed GCF. Also. the effect of reactive power compensation is illustrated in same systems.

• Aerospace Engineering and Technology
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• v.9 no.2
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• pp.57-62
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• 2010

SAR payload of LEO satellite will consume about 150A current. This high current makes the voltage drop between battery, satellite main bus and payload interface, which cannot guarantee the input voltage level of the satellite electrical unit and payload. So, it is necessary to predict the main bus and payload input voltage level when the payload works. In this paper, the worst case analysis of the harness and contact resistance was executed and predicted the voltage drop when the payload works.

• Journal of Power Electronics
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• v.16 no.4
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• pp.1256-1267
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• 2016

Distributed stray inductance exerts a significant influence on the turn-off voltages of power switching devices. Therefore, the design of low stray inductance bus bars has become an important part of the design of high-power converters. In this study, we first analyze the operational principle and switching transient of a T-type converter. Then, we obtain the commutation circuit, categorize the stray inductance of the circuit, and study the influence of the different types of stray inductance on the turn-off voltages of switching devices. According to the current distribution of the commutation circuit, as well as the conditions for realizing laminated bus bars, we laminate the bus bar of the converter by integrating the practical structure of a capacitor bank and a power module. As a result, the stray inductance of the bus bar is reduced, and the stray inductance in the commutation circuit of the converter is reduced to more than half. Finally, a 10 kVA experimental prototype of a T-type converter is built to verify the effectiveness of the designed laminated bus bar in restraining the turn-off voltage spike of the switching devices in the converter.

• Journal of Power Electronics
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• v.17 no.5
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• pp.1244-1255
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• 2017

The space vector pulse width modulation (SVPWM) technique is a popular PWM method for medium voltage drive applications. Conventional SVPWM (CSVPWM) and bus clamped SVPWM (BCSVPWM) are the most common SVPWM techniques. This paper evaluates the performance of various advanced BCSVPWM strategies in terms of their harmonic distortion and switching loss based on a uniform frame work. A uniform frame work, pulse number captures the performance parameter variations of different SVPWM strategies for various number of samples with heterogeneous pulse numbers. This work compares different advanced BCSVPWM techniques based on the modulation index and location of the clamping position (zero vector changing angle ) of a phase in a line cycle. The frame work provides a fixed fundamental frequency of 50Hz. The different BCSVPWM switching strategies are implemented and compared experimentally on a 415V, 2.2kW, 50Hz, 3-phase induction motor drive which is fed from an IGBT based 2 KVA voltage source inverter (VSI) with a DC bus voltage of 400 V. A low cost PIC microcontroller (PIC18F452) is used as the controller platform.