• Journal of Satellite, Information and Communications
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• v.8 no.4
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• pp.75-80
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• 2013

In this paper, the Ka-band maritime satellite communication systems for mobile terminals are proposed. The design includes the link budget analysis, determination of modulation and coding schemes and the overall structure of a transmitter. To avoid the harmful effects on the existing DVB-S2 services, the proposed maritime satellite system using the same spectrum with DVB-S2 at the same time employs the very wideband spreading transmission. Additionally, omni-directional low-gain antennas should be equipped in a mobile terminal to reduce the system cost. These two considerations limit the maximum transmission rate of the proposed system. Due to the limitations, the proposed system includes 36 dB or 39 dB spreading gain depending on the modulation scheme and a link-adaptive repetition method depending on the level of rain attenuation. To support short packets with minimal performance loss, the turbo code used in 3GPP instead of LDPC(low density parity check code) is adopted. By combining them, the overall structure of low-rate maritime satellite communication system is designed.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.6
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• pp.1255-1260
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• 2011

In this paper, we study on the reliability of Very High-rate Power Line Communication (VH-PLC) for Smart Grid, so that the resultant data rate is over 400Mbps at a physical layer. Firstly, reviewing the research trend of the PLC, we discuss the required techniques for supporting the Smart Grid. Considering a pre-specification with the value of several parameters, we investigate a multi-carrier modulation technique to overcome limitations of higher rate transmission under power line channel environments. Then, we propose a system specification of the VH-PLC in the sense of enhancing two features. One is resolving the problem of the co-existence of the deployed high-speed PLC according to the published standardization of KS X 4600-1 in Korea. The other is getting better performance on the grid adopting the diverse element techniques, such as multi-carrier modulation, a subcarrier utilization mode, a variable rate LDPC (Low Density Parity Check) code, and a time and frequency diversity technique. Further, a simulation tool, composed of an Event-Driven simulator and a Time-Driven simulator, is developed for the purpose of verifying the system performance and continuously cross-checking the test bench signal of the proposed VH-PLC system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.4
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• pp.659-665
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• 2015

Recent studies on network coding scheme for increasing transmission efficiency of the network has been actively conducted. In this paper, we apply RLNC in sub-packet unit and propose a joint scheme of sub-packet level network coding and LDPC code. The proposed method can have similar ability of network coding and obtain further error correction capability. The simulation results show that the proposed one enhances error correction capability compared to the case using only LDPC when extra packets are received.

• Journal of Navigation and Port Research
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• v.36 no.8
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• pp.631-635
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• 2012

Underwater acoustic communication has multipath error because of reflection by sea-level and sea-bottom. The multipath of underwater channel causes signal distortion and error floor. In this paper, in order to design an efficient packet structure, we employ channel coding scheme and phase recovery algorithm. For channel coding scheme, half rate LDPC channel coding scheme with N=1944 and K=972 was used. Also, decision directed phase recovery was used for correcting phase offset induced by multipath. Based on these algorithms, we propose length of data for optimal packet structure in the environment of oceanic experimentation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.486-489
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• 2010

This paper describes a layered LDPC decoder which supports block length of 1,944 bits and code rate 1/2 for IEEE 802.11n WLAN standard. To reduce the hardware complexity, the min-sum algorithm and layered architecture is adopted. A novel memory reduction technique suitable for min-sum algorithm reduces memory size by 75% compared with conventional method. The designed processor has 200,400 gates and 19,400 bits memory, and it is verified by FPGA implementation. The estimated throughput is about 200 Mbps at 120 MHz clock by using Xilinx Virtex-4 FPGA device.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.10C
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• pp.923-929
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• 2003

Turbo processing have been known as methods close to Shannon limit in the aspect of wireless multi-input multi-output (MIMO) communications similarly to wireless single antenna communication. The iterative processing can maximize the mutual effect of coding and interference cancellation, but LDPC coding has not been used for turbo processing because of the inherent decoding process delay. This paper suggests a LDPC coded MIMO system with turbo parallel space-time (Turbo-PAST) processing for high-speed wireless communications and proposes a average soft-output syndrome (ASS) check scheme at low signal to noise ratio (SNR) for the Turbo-PAST system to decide the reliability of decoded frame. Simulation results show that the suggested system outperforms conventional system and the proposed ASS scheme effectively reduces the amount of turbo processing iterations without performance degradation from the point of average number of iterations.

• Journal of Broadcast Engineering
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• v.16 no.6
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• pp.1026-1035
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• 2011

This paper presents generalization and application for the conventional SISO decoding algorithm of Block Turbo Codes. R. M. Pyndiah suggested an iterative SISO decoding algorithm for Product Codes, two-dimensionally combined linear block codes, on AWGN channel. It wascalled Block Turbo Codes. Based on decision of Chase algorithm which is SIHO decoding method, SISO decoder for BTC computes soft decision information and transfers the information to next decoder for iterative decoding. Block Turbo Codes show Shannon limit approaching performance with a little iteration at high code rate on AWGN channel. In this paper we generalize the conventional decoding algorithm of Block Turbo Codes, under BPSK modulation and AWGN channel transmission assumption, to the LLR value based algorithm and suggest an application example such as concatenated structure of LDPC codes and Block Turbo Codes.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.5C
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• pp.423-431
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• 2010

In this paper, a modified sum-product algorithm to correct bit errors captured within the trapping sets, which are produced in decoding of low-density parity-check (LDPC) codes, is proposed. Unlike the original sum-product algorithm, the proposed decoding method consists of two stages. Whether the main cause of decoding failure is the trapping sets or not is determined at the first stage. And the bit errors within the trapping sets are corrected at the second stage. In the modified algorithm, the set of failed check nodes and the transition patterns of hard-decision bits are exploited to search variable nodes in the trapping sets. After inverting information of the variable nodes, the sum-product algorithm is carried out to correct the bit errors. As a result of simulation, the proposed algorithm shows continuously improved error performance with increase in the signal-to-noise ratio. It is, therefore, considered that the modified sum-product algorithm significantly reduces or possibly eliminates the error floor in LDPC codes.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.11
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• pp.1248-1255
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• 2012

LDPC decoder architectures are generally classified into serial, parallel and partially parallel architectures. Conventional method of LDPC decoding in general give rise to a large number of computation operations, mass power consumption, and decoding delay. It is necessary to reduce the iteration numbers and computation operations without performance degradation. This paper studies horizontal shuffle scheduling(HSS) algorithm and self-correction normalized min-sum(SC-NMS) algorithm. In the result, number of iteration is half than conventional algorithm and performance is almost same between sum-product(SP) and SC-NMS. Finally, This paper implements high-speed LDPC decoder based on FPGA. Decoding throughput is 816 Mbps.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.5B
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• pp.573-581
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• 2011

The underwater channel is known to offer poor communications channel. The channel medium is highly absorptive and the transmission bandwidth is limited. In addition, the channel is highly frequency selective; the degree of selectiveness depends on a detailed geometry of the channel. Furthermore, the response changes over time as the channel conditions affecting the response such as water temperature, sea surface wind and salinity are time-varying. The transceiver design to deal with the frequency and time selective channel, therefore, becomes very challenging. It has been known that deep fading at certain specific sub-carriers are detrimental to OFDM systems. To mitigate this negative effect, the proposed coded OFDM system employs an LDPC code based modulation. In this paper, we aim 1) to provide a detailed underwater channel model; 2) to design a robust LDPC coded OFDM system; 3) to test the proposed system under a variety of channel conditions enabled by the channel model.