• Title/Summary/Keyword: Low Density Parity Check Code(LDPC)

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Performance of LDPC Decoder of HSS based on Non-Uniform Quantization (비균일 양자화 방식 기반 HSS 방식의 LDPC 복호기 성능)

  • Kim, Tae-Hun;Kwon, Hae-Chan;Jung, Ji-Won
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.17 no.9
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    • pp.2029-2035
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    • 2013
  • In this paper, we presented non-uniform quantization method for LDPC decoder specified in DVB-S2 standard. There are some problems in order to implement LDPC decoder in aspect to algorithm and implementation. In algorithm aspect, because of large number of iterations, LDPC decoding in general give rise to a large number of computation operations, mass power consumption, and decoding delay. Therefore, this paper studies Horizontal Shuffle Scheduling (HSS) algorithm which reduced iteration number without performance loss. In aspect of implementation, there are some solutions to improve the decoding speed, however this paper focused on non-uniform quantization which reduce the quantization bits of LDPC decoder. In simulation results, Decoding throughput of HSS LDPC decoder based on non-uniform quantization is 816Mbps and it improved 12% compared to conventional one.

Implementation of LDPC Decoder using High-speed Algorithms in Standard of Wireless LAN (무선 랜 규격에서의 고속 알고리즘을 이용한 LDPC 복호기 구현)

  • Kim, Chul-Seung;Kim, Min-Hyuk;Park, Tae-Doo;Jung, Ji-Won
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.14 no.12
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    • pp.2783-2790
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    • 2010
  • In this paper, we first review LDPC codes in general and a belief propagation algorithm that works in logarithm domain. LDPC codes, which is chosen 802.11n for wireless local access network(WLAN) standard, require a large number of computation due to large size of coded block and iteration. Therefore, we presented three kinds of low computational algorithms for LDPC codes. First, sequential decoding with partial group is proposed. It has the same H/W complexity, and fewer number of iterations are required with the same performance in comparison with conventional decoder algorithm. Secondly, we have apply early stop algorithm. This method reduces number of unnecessary iterations. Third, early detection method for reducing the computational complexity is proposed. Using a confidence criterion, some bit nodes and check node edges are detected early on during decoding. Through the simulation, we knew that the iteration number are reduced by half using subset algorithm and early stop algorithm is reduced more than one iteration and computational complexity of early detected method is about 30% offs in case of check node update, 94% offs in case of check node update compared to conventional scheme. The LDPC decoder have been implemented in Xilinx System Generator and targeted to a Xilinx Virtx5-xc5vlx155t FPGA. When three algorithms are used, amount of device is about 45% off and the decoding speed is about two times faster than convectional scheme.

A Modified Sum-Product Algorithm for Error Floor Reduction in LDPC Codes (저밀도 패리티 검사부호에서 오류마루 감소를 위한 수정 합-곱 알고리즘)

  • Yu, Seog-Kun;Kang, Seog-Geun;Joo, Eon-Kyeong
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.35 no.5C
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    • pp.423-431
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    • 2010
  • In this paper, a modified sum-product algorithm to correct bit errors captured within the trapping sets, which are produced in decoding of low-density parity-check (LDPC) codes, is proposed. Unlike the original sum-product algorithm, the proposed decoding method consists of two stages. Whether the main cause of decoding failure is the trapping sets or not is determined at the first stage. And the bit errors within the trapping sets are corrected at the second stage. In the modified algorithm, the set of failed check nodes and the transition patterns of hard-decision bits are exploited to search variable nodes in the trapping sets. After inverting information of the variable nodes, the sum-product algorithm is carried out to correct the bit errors. As a result of simulation, the proposed algorithm shows continuously improved error performance with increase in the signal-to-noise ratio. It is, therefore, considered that the modified sum-product algorithm significantly reduces or possibly eliminates the error floor in LDPC codes.

Underwater Channel Analysis and Transmission Method Research via Coded OFDM (수중채널 분석과 Coded OFDM을 통한 전송방법 연구)

  • Jeon, Hyeong-Won;Lee, Su-Je;Lee, Heung-No
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.36 no.5B
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    • pp.573-581
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    • 2011
  • The underwater channel is known to offer poor communications channel. The channel medium is highly absorptive and the transmission bandwidth is limited. In addition, the channel is highly frequency selective; the degree of selectiveness depends on a detailed geometry of the channel. Furthermore, the response changes over time as the channel conditions affecting the response such as water temperature, sea surface wind and salinity are time-varying. The transceiver design to deal with the frequency and time selective channel, therefore, becomes very challenging. It has been known that deep fading at certain specific sub-carriers are detrimental to OFDM systems. To mitigate this negative effect, the proposed coded OFDM system employs an LDPC code based modulation. In this paper, we aim 1) to provide a detailed underwater channel model; 2) to design a robust LDPC coded OFDM system; 3) to test the proposed system under a variety of channel conditions enabled by the channel model.

차세대 통신 시스템을 위한 오류 정정 부호

  • Park, Ho-Seong;No, Jong-Seon
    • Information and Communications Magazine
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    • v.29 no.8
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    • pp.26-33
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    • 2012
  • 차세대 통신 시스템에서는 고속 데이터 전송을 위해 다수의 송신자와 수신자가 네트워크를 구성하여 정보를 주고 받는 다자간 협력 통신을 가정한다. 이러한 상황에 적합한 오류 정정 부호로 이미 탁월한 오류 정정 능력을 검증 받은 저밀도 패리티 체크 (low-density parity-check, LDPC)부호, 이진 입력 이산 비기억 (discrete memoryless) 채널에서 무한한 길이에 대하여 채널 용량 (channel capacity)을 달성하는 것으로 알려진 극 부호 (polar code), 아직은 많이 개발되지 않았지만 보다 높은 전송률을 달성할 수 있는 다중점 (multiple point) 채널에서의 새로운 부호 등이 거론될 수 있다. 본고에서는 이러한 차세대 통신 시스템을 위한 오류 정정 부호들에 대해서 기본 이론과 최근 연구 동향, 그리고 향후 연구 방향 등을 소개하도록 한다.

Performance Evaluation of Error Correcting Code through DVB-C2 Channel Encode/Decode Simulator (DVB-C2 채널 부복호 시뮬레이터를 통한 오류정정 부호 성능 검증)

  • Jung, Joon-Young;Choi, Dong-Joon;Hur, Namho
    • Proceedings of the Korean Society of Broadcast Engineers Conference
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    • 2011.07a
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    • pp.272-274
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    • 2011
  • 최근 들어 케이블 방송망을 기반으로 한 디지털 방송, VoIP(Voice over Internet Protocol), VOD(Video on Demand), 영상전화, 이동전화, 무선 랜 로밍 등의 다양한 멀티미디어 서비스의 출현과 향후 도입될 새로운 융합형 멀티미디어 서비스의 수용을 위해 케이블 망의 고도화에 대한 요구가 제기되었다. 특히 유럽을 중심으로 이러한 요구를 만족시키기 위해 DVB(Digital Video Broadcasting)-C2 규격의 개발이 진행되었다. DVB-C2 규격에서는 기존의 게이블 전송 규격인 DVB-C에 대해 30% 이상의 전송 효율을 높이고자 새로운 변조 방식과 채널 오류정정 부호 방식을 도입하였다. 이에 본 논문은 본 논문에서는 DVB-C2 규격에서 도입된 채널 오류정정 부호인 BCH(Bose, Chaudhuri, and Hocquenghem) 부호와 LDPC(Low Density Parity Check) 부호의 연접 방식에 대한 성능을 검증하고자 한다. 이를 위해 개발된 시뮬레이터의 소개와 이를 통한 시험결과를 제시한다.

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LLR Based Generalization of Soft Decision Iterative Decoding Algorithms for Block Turbo Codes (LLR 기반 블록 터보 부호의 연판정 복호 알고리즘 일반화)

  • Im, Hyun-Ho;Kwon, Kyung-Hoon;Heo, Jun
    • Journal of Broadcast Engineering
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    • v.16 no.6
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    • pp.1026-1035
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    • 2011
  • This paper presents generalization and application for the conventional SISO decoding algorithm of Block Turbo Codes. R. M. Pyndiah suggested an iterative SISO decoding algorithm for Product Codes, two-dimensionally combined linear block codes, on AWGN channel. It wascalled Block Turbo Codes. Based on decision of Chase algorithm which is SIHO decoding method, SISO decoder for BTC computes soft decision information and transfers the information to next decoder for iterative decoding. Block Turbo Codes show Shannon limit approaching performance with a little iteration at high code rate on AWGN channel. In this paper we generalize the conventional decoding algorithm of Block Turbo Codes, under BPSK modulation and AWGN channel transmission assumption, to the LLR value based algorithm and suggest an application example such as concatenated structure of LDPC codes and Block Turbo Codes.

Study on Very High-Rate Power Line Communications for Smart Grid (스마트그리드를 위한 초고속 전력선통신기술 연구)

  • Choi, Sung-Soo;Oh, Hui-Myoung;Kim, Young-Sun;Kim, Yong-Hwa
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.60 no.6
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    • pp.1255-1260
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    • 2011
  • In this paper, we study on the reliability of Very High-rate Power Line Communication (VH-PLC) for Smart Grid, so that the resultant data rate is over 400Mbps at a physical layer. Firstly, reviewing the research trend of the PLC, we discuss the required techniques for supporting the Smart Grid. Considering a pre-specification with the value of several parameters, we investigate a multi-carrier modulation technique to overcome limitations of higher rate transmission under power line channel environments. Then, we propose a system specification of the VH-PLC in the sense of enhancing two features. One is resolving the problem of the co-existence of the deployed high-speed PLC according to the published standardization of KS X 4600-1 in Korea. The other is getting better performance on the grid adopting the diverse element techniques, such as multi-carrier modulation, a subcarrier utilization mode, a variable rate LDPC (Low Density Parity Check) code, and a time and frequency diversity technique. Further, a simulation tool, composed of an Event-Driven simulator and a Time-Driven simulator, is developed for the purpose of verifying the system performance and continuously cross-checking the test bench signal of the proposed VH-PLC system.

Design of Maritime Satellite Communication Systems Sharing Frequency with DVB-S2 (DVB-S2와 주파수 공유하는 해양 위성 통신 시스템 설계)

  • Ryu, Joon-Gyu;Oh, Deock-Gil;Yu, Heejung
    • Journal of Satellite, Information and Communications
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    • v.8 no.4
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    • pp.75-80
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    • 2013
  • In this paper, the Ka-band maritime satellite communication systems for mobile terminals are proposed. The design includes the link budget analysis, determination of modulation and coding schemes and the overall structure of a transmitter. To avoid the harmful effects on the existing DVB-S2 services, the proposed maritime satellite system using the same spectrum with DVB-S2 at the same time employs the very wideband spreading transmission. Additionally, omni-directional low-gain antennas should be equipped in a mobile terminal to reduce the system cost. These two considerations limit the maximum transmission rate of the proposed system. Due to the limitations, the proposed system includes 36 dB or 39 dB spreading gain depending on the modulation scheme and a link-adaptive repetition method depending on the level of rain attenuation. To support short packets with minimal performance loss, the turbo code used in 3GPP instead of LDPC(low density parity check code) is adopted. By combining them, the overall structure of low-rate maritime satellite communication system is designed.

Performance Analysis of a Bit Mapper of the Dual-Polarized MIMO DVB-T2 System (이중 편파 MIMO를 쓰는 DVB-T2 시스템의 비트 매퍼 성능 분석)

  • Kang, In-Woong;Kim, Youngmin;Seo, Jae Hyun;Kim, Heung Mook;Kim, Hyoung-Nam
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.38A no.9
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    • pp.817-825
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    • 2013
  • The UHDTV system, which provides realistic service with ultra-high definite video and multi-channel audio, has been studied as a next generation broadcasting service. Since the conventional digital terrestrial transmission system is not capable to cover the increased transmission data rate of the UHDTV service, there are great necessity of researches about increase of data rate. Accordingly, the researches has been studied to increase the transmission data rate of the DVB-T2 system using dual-polarized MIMO technique and high order modulation. In order to optimize the MIMO DVB-T2 system where irregular LDPC codes are used, it is necessary to study the design of the bit mapper that matches the LDPC code and QAM symbols in MIMO channel. However, the research related to the design of the bit mapper has been limited to the SISO system. Therefore, this paper defines a new parameter that indicates the VND distribution of MIMO DVB-T2 system and performs the performance analysis according to the parameter which will be helpful for designing a MIMO bit mapper.