• Journal of electromagnetic engineering and science
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• v.11 no.2
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• pp.105-112
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• 2011

In phase-locked frequency synthesizers, a fast-lock technique is frequently employed to overcome the trade-off between a lock-time and a spurious response. The function of fast-lock in a conventional PLL (Phased Lock Loop) IC (Integrated Circuit) is limited by a factor of 16, which is usually implemented by a scaling of charge pumper, and consequently a lock time improvement of a factor of 4 is possible using the conventional PLL IC. In this paper, we propose a novel external active fast-lock loop filter. The proposed loop filter provides, conceptually, an unlimited scaling of charge pumper current, and can overcome conventional trade-off between lock-time and spur suppression. To demonstrate the validity of our proposed loop-filter, we fabricated an X-band frequency synthesizer using the proposed loop filter. The loop filter in the synthesizer is designed to have a loop bandwidth of 100 kHz in the fast-lock mode and a loop bandwidth of 5 kHz in the normal mode, which corresponds to a charge pumper current change ratio of 400. The X-band synthesizer shows successful performance of a lock-time of below 10 ${\mu}sec$ and reference spur suppression below -64 dBc.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.36 no.6
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• pp.1059-1068
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• 2016

The current operation method for the AVC (Automatic Vehicle Classification) equipment does not generate vehicle speed, traffic volume and vehicle type information when part of the sensors has failed. Inefficiency of current methods would not use the collected data from the normal sensor. In this study was conducted research on the calculating method at the traffic volume and vehicle speed in the sensor failure AVC equipment. The failure situation of the sensor was classified into 4 types. Calculating the traffic volume and vehicle speed information for each type, and accuracy of these informations were analyzed. Analysis results, traffic volume was possible to calculate a highly accurate value (accuracy: 100%, 98%, 97%). In the case of speed, the accuracy of the calculated speed value reaches a level that can be accepted sufficiently (RMSE value is less than 16.8). So, using the methodology proposed in this study are expected to be able to increase the operational efficiency of the AVC equipment.

• Nuclear Engineering and Technology
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• v.30 no.6
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• pp.531-540
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• 1998

The DYLAM-3 code which overcomes the limitation of event tree/fault tree was applied to LOOP (Loss of Off-site Power) in the mid-loop operation employing HEPs (Human Error Probabilities) supplied by the ASEP (Accident Sequence Evaluation Program) and the SEPLOT (Systematic Evaluation Procedure for Low power/shutdown Operation Task) procedure in this study. Thus the time history of core uncovery frequency during the mid-loop operation was obtained. The sensitivity calculations in the operator's actions to prevent core uncovery under LOOP in the mid-loop operation were carried out. The analysis using the time dependent HEP was performed on the primary feed & bleed which has the most significant effect on core uncovery frequency. As the result, the increment of frequency is shown after 200 minutes duration of simulation conditions. This signifies the possibility of increment in risk after 200 minutes. The primary feed & bleed showed the greatest impact on core uncovery frequency and the recovery of the SCS (Shutdown Cooling System) showed the least impact. Therefore the efforts should be taken on the primary feed & bleed to reduce the core uncovery frequency in the mid-loop operation. And the capability of DYLAM-3 in applying to the time dependent concerns could be demonstrated.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.10
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• pp.1104-1111
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• 2003

The paper presents an algorithm for the compensation of gain and phase imbalances to exist between I-phase and Q-phase signal at direct conversion receiver. We propose a gain and phase imbalances blind equalization compensation algorithm by using variable step-size adaptive loop at direct conversion receiver. The blind equalization schemes have trade-off between convergence speed and jitter effect for the compensation of gain and phase imbalance. We propose the variable step-size adaptive loop method, which varies the loop coefficients according to errors, for recovering these problem. By using variable step-size adaptive loops, we propose to speed up the convergence process and reduce the jitter effect and simulation results show that the algorithm compensates signal loss and speeds up convergence time.

• The Transactions of the Korean Institute of Power Electronics
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• v.24 no.3
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• pp.191-200
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• 2019

This study proposes a hardware-in-the-loop simulation (HILS) system based on National Instruments' PXI platform to test power management and operation strategies for DC microgrids (MGs). The HILS system is developed based on the controller HIL prototype, which involves testing the controller board in hardware with a real-time simulation model of the plant in a real-time digital simulator. The system provides an economical and effective testing function for research on MG systems. The decentralized power management strategy based on the DC bus signaling method for DC MGs has been developed and implemented on the HILS platform. HILS results are determined to be similar to those of the off-line simulation in PSIM software.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.3
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• pp.376-380
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• 1987

The closed-loop transfer function of 2-nd order PLL (phase-looked loop)of which loop filter has active-lag 1-st order is found. Considering the three criteria of system performance: the transient response time of the circuit, noise bandwidth by the linear analysis and stability which uses root-locus method, the optimum value of damping factor is 1.0 and the natural frequency which depends upon the signal frequency can be determined after consideration of the trade-off relationship between the transient response time and the noise bandwidth.

• The Bulletin of The Korean Astronomical Society
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• v.46 no.1
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• pp.43.2-43.2
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• 2021

In this study, we report oscillations of the total intensity of white light loops in the off-limb solar flare observed in 2017-Sep-10 with the SDO/HMI. The total intensity oscillations are correlated with the area of the flaring loop in the plane of the sky. The oscillatory pattern is well fitted by two consecutive damped oscillations. The period and damping time of the first oscillation are 12.9 minutes and 9.9 minutes, respectively. Those of the second oscillation are 11.7 minutes and 15.4 minutes. The excitation of the oscillations coincides with two consecutive type III radio bursts observed in meter range. Assuming the oscillations are magnetoacoustic waves in the flaring loops with the loop lengths ranging from 30 to 90 Mm, the temperature of the white light emitting loops could be in the range from 0.3 MK to 2.6 MK.

• 제어로봇시스템학회:학술대회논문집
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• 1996.10b
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• pp.164-167
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• 1996

This paper presents an off-line P.I.D parameter estimation method during normal operation in power plant. The process parameters are estimated using the recursive least square method. The controller parameters are estimated on the basis of desired characteristics of the dynamic model of the closed-loop control.

• ETRI Journal
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• v.29 no.4
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• pp.463-469
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• 2007

A phase-locked loop (PLL) is described which is operable from 0.4 GHz to 1.2 GHz. The PLL has basically the same architecture as the conventional analog PLL except the locking information is stored as digital code. An analog-to-digital converter is embedded in the PLL, converting the analog loop filter output to digital code. Because the locking information is stored as digital code, the PLL can be turned off during power-down mode while avoiding long wake-up time. The PLL implemented in a 0.18 ${\mu}m$ CMOS process occupies 0.35 $mm^2$ active area. From a 1.8 V supply, it consumes 59 mW and 984 ${\mu}W$ during the normal and power-down modes, respectively. The measured rms jitter of the output clock is 16.8 ps at 1.2 GHz.

• Journal of Power Electronics
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• v.18 no.3
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• pp.892-901
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• 2018

SiC MOSFETs have been used to improve system efficiency in high frequency converters due to their extremely high switching speed. However, this can result in undesirable parasitic oscillations in practical systems. In this paper, models of the key components are introduced first. Then, theoretical formulas are derived to calculate the switching oscillation frequencies after full turn-on and turn-off in clamped inductive circuits. Analysis indicates that the turn-on oscillation frequency depends on the power loop parasitic inductance and parasitic capacitances of the freewheeling diode and load inductor. On the other hand, the turn-off oscillation frequency is found to be determined by the output parasitic capacitance of the SiC MOSFET and power loop parasitic inductance. Moreover, the shifting regularity of the turn-off maximum peak voltage with a varying switching speed is investigated on the basis of time domain simulation. The distortion of the turn-on current is theoretically analyzed. Finally, experimental results verifying the above calculations and analyses are presented.