• The Transactions of the Korean Institute of Power Electronics
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• v.14 no.4
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• pp.278-284
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• 2009

This paper presents a firing angle controller of a thyristor converter for DC power supply using PID controller with parallel data loop to improve the dynamic response. The proposed parallel data loop for firing angle controller of 3-phase semi-converter, generates pre-measured firing angle according to reference voltage and load current. With the approximated firing angle according to operating conditions, the output voltage can fast keep the reference value with small voltage error. And the PID controller compensates the output voltage error from the firing angle of parallel data loop. In order to reduce the sudden changing of the data from current ripple, a simple digital low pass filter is used to determine the output data. The proposed control scheme is verified by the experimental test of a practical 50[A] grade thyristor converter system.

• Journal of Power Electronics
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• v.18 no.6
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• pp.1659-1669
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• 2018

An improved circulating current suppression control method is proposed in this paper. In the proposed controller, an outer loop of the average capacitor voltage control model is used to balance the sub-module capacitor voltage. Meanwhile, an individual voltage balance controller and an arm voltage balance controller are also used. The DC and harmonic components of the circulating current are separated using a low pass filter. Therefore, a multiple quasi-proportional-resonant (multi-quasi-PR) controller is introduced in the inner loop to eliminate the circulating harmonic current, which mainly contains second-order harmonic but also contains other high-order harmonics. In addition, the parameters of the multi-quasi-PR controller are designed in the discrete domain and an analysis of the stability characteristic is given in this paper. In addition, a simulation model of a three-phase MMC system is built in order to confirm the correctness and superiority of the proposed controller. Finally, experiment results are presented and compared. These results illustrate that the improved control method has good performance in suppressing circulating harmonic current and in balancing the capacitor voltage.

• Proceedings of the KIPE Conference
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• 2015.07a
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• pp.397-398
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• 2015

본 논문은 $LiFePO_4$ 셀의 SOC(State of Charge) 추정에서 가장 중요한 역할을 하는 모델 파라미터인 OCV(Open Circuit Voltage)의 설계에 관한 것이다. $LiFePO_4$ 셀은 히스테리시스 특성 때문에 Charging/Discharging OCV값을 이은 curve인 Major loop만으로는 신뢰도 높은 SOC 추정이 어렵다. 따라서, 기존의 Major loop에 추가적으로 SOC 10% 구간별로 Minor loop을 설계해 줌으로써 배터리 모델링의 정확도를 높이고, 이를 최종적으로 EKF(Extended Kalman Filter)알고리즘을 이용하여 SOC 추정으로 해봄으로써 정확도 향상을 비교해 보고 분석해 보고자 한다.

• Journal of Power Electronics
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• v.15 no.1
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• pp.216-226
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• 2015

Grid synchronization is one of the key techniques for the grid-connected power converters used in distributed power generation systems. In order to achieve fast and accurate grid synchronization, a new phase locked loop (PLL) is proposed on the basis of the complex filter matrixes (CFM) orthogonal signal generator (OSG) crossing-decoupling method. By combining first-order complex filters with relation matrixes of positive and negative sequence voltage components, the OSG is designed to extract specific frequency orthogonal signals. Then, the OSG mathematical model is built in the frequency-domain and time-domain to analyze the spectral characteristics. Moreover, a crossing-decoupling method is suggested to decouple the fundamental voltage. From the eigenvalue analysis point of view, the stability and dynamic performance of the new PLL method is evaluated. Meanwhile, the digital implementation method is also provided. Finally, the effectiveness of the proposed method is verified by experiments under unbalanced and distorted grid voltage conditions.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.10
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• pp.1147-1158
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• 2008

In this paper, we designed a phase-looking circuit that locks the 16.8 GHz VTDRO to a 700 MHz SAW oscillator using SPD as a phase detector Direct phase locking with loop filter alone causes the problem of lock time, so VTDRO is phase leered by loop filter with the aid of time varying square wave current generator. The current generator is related to the loop filter and needs the systematic toning. In this paper, a systematic design of the current generator and loop filter is presented. The fabricated PLDRO shows a stabilized frequency of 16.8 GHz, a output power 6.3 dBm, and a phase noise of -101 dBc/Hz at the 100 kHz offset.

• Proceedings of the KIEE Conference
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• 2000.07b
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• pp.1233-1235
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• 2000

A new control method of three phase converter without measuring input phase-voltage and DC-link voltage is proposed. Input phase-voltage of these required voltages is estimated using EKF(Extended Kalman Filter) and DC-link voltage is estimated from the measured line currents and the estimated input phase-voltage. This control method is achieved without PLL(Phase Locked Loop) which senses the angle of input phase-voltage and DC-link voltage sensor. In addition, the proposed method controls high power factor and DC-link voltage utilizing the estimated phase angle. This paper describes the effectiveness of the proposed estimated algorithm through simulations.

• Proceedings of the KIPE Conference
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• 2001.07a
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• pp.227-230
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• 2001

A new control method of three phase converter without measuring input Phase-voltage and DC-link voltage is Proposed. Input Phase-voltage of these required voltages is estimated using EKF(Extended Kalman Filter) and DC-link voltage is estimated from the measured line currents and the estimated input phase-voltage. This control method is achieved without PLL(Phase Locked Loop) which senses the angle of input phase-voltage and DC-link voltage sensor. In additon, the proposed method controls high power factor and DC-link voltage utilizing the estimated phase angle. This paper describes the effectiveness of the proposed estimated algorithm through simulations.

• Proceedings of the Korean Society of Marine Engineers Conference
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• 2005.06a
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• pp.1005-1010
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• 2005

In this paper, it is presented a frequency modulated continuous wave radar (FMCW) for distance measurement. The frequency range is $10{\sim}11$ GHz and the sweep time of the signal is 100 ms. The test target is 0.8 m2 of metal plate. The experiment is performed in open ground and the pyramidal horn antenna of about 22 dBi gain is used. The beat frequency according to the target moving to 40 m is measured. There is a good agreement between measured and calculated results. But the resolution of the FMCW radar is not good such as about 10 cm. It is result from the nonlinear signal of voltage controlled oscillator (VCO). To improve the nonlinear characteristic of VCO, a high pass filter and phase locked loop (PLL) frequency synthesizer are included in the radar system.

• Progress in Superconductivity
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• v.7 no.1
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• pp.46-51
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• 2005

We have developed control electronics to operate flux-locked loop (FLL), and analog signal filters to process FLL outputs for 64-channel Double Relaxation Oscillation SQUID (DROS) magnetocardiography (MCG) system. Control electronics consisting of a preamplifier, an integrator, and a feedback, is compact and low-cost due to larger swing voltage and flux-to-voltage transfer coefficients of DROS than those of dc SQUIDs. Analog signal filter (ASF) serially chained with a high-pass filter having a cut-off frequency of 0.1 Hz, an amplifier having a gain of 100, a low-pass filter of 100 Hz, and a notch filter of 60 Hz makes FLL output suitable for MCG. The noise of a preamplifier in FLL control electronics is $7\;nV/{\surd}\;Hz$ at 1 Hz, $1.5\;nV/{\surd}\;Hz$ at 100 Hz that contributes $6\;fT/{\surd}\;Hz$ at 1 Hz, $1.3\;fT/{\surd}\;Hz$ at 100 Hz in readout electronics, and the noise of ASF electronics is $150\;{\mu}V/{\surd}\;Hz$ equivalent to $0.13\;fT/{\surd}\;Hz$ within the range of $1{\sim}100\;Hz$. When DROSs are connected to readout electronics inside a magnetically shielded room, the noise of 64-channel DROS system is $10\;fT/{\surd}\;Hz$ at 1 Hz, $5\;fT/{\surd}\;Hz$ at 100 Hz on the average, low enough to measure human MCG.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.313-321
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• 2014

A low-power low-cost polar transmitter for EDGE is designed in $0.18{\mu}m$ CMOS. A differential delta-sigma modulator (DSM) tunes a three-terminal voltage-controlled oscillator (VCO) to perform RF phase modulation, where the VCO tuning curve is digitally pre-compensated for high linearity and the carrier frequency is calibrated by a dual-mode low-power frequency-locked loop (FLL). A digital intermediate-frequency (IF) pulse-width5 modulator (PWM) drives a complementary power-switch followed by an LC filter to achieve envelope modulation with high efficiency. The proposed transmitter with 9mW power dissipation relaxes the time alignment between the phase and envelope modulations, and achieves an error vector magnitude (EVM) of 4% and phase noise of -123dBc/Hz at 400kHz offset frequency.