• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.8
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• pp.28-34
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• 2008

A magnetic field detector as a potential MRI receiver is proposed. The proposed device is composed of SRR(split ring resonator) which is a kind of LC resonator first introduced as a negative permeability material and a simple loop antenna. The proposed device showed similar degree of performance to commercial one with a simpler circuit.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.16 no.6
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• pp.102-108
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• 2002

This paper handles the design of a real time traffic data acquisition system using loop detector and piezo-electric sensor to acquire the vehicle information EISA compatible parallel I/O interface card is designed to sample 30 I/O channels at variable rates for raw traffic data acquisition. The control software is designed to generate the traffic data informations from the raw data. The traffic data information provides vehicle length, speed, number of axles, etc. Vehicle types are detected and categorized into eleven types from the vehicle length, axles positions and axle counts information. The traffic information is formed into packet and transferred to the remote hosts through serial communications for ITS applications.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.26 no.2
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• pp.44-50
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• 2012

When the fiber Bragg gratings are embedded in a fiber-optic Sagnac loop for measuring temperature or strain, it is difficult to separate the Bragg wavelengths. The transmitted light is mixed with the reflected Bragg wavelengths in the photo-detector, working as noises. To suppress the noises, we placed the FBG sensors and a fiber-optic attenuator at asymmetric positions in the loop. With the arrangement the reflected light became much bigger than the transmitted light, enabling the separation of the reflected Bragg wavelengths with almost the same signal-to-noise ratio of the FBG sensors outside the loop.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.5
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• pp.605-615
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• 1986

The phase-locked loop(PLL) is a communication receiver which operates as a coherent detector by continuously correcting the phase error. In this paper analysis for the Phase-error behavior of analog phase-locked loop (APLL) in the presence of additive white gaussian noise has been done theoretically and experimentally. A close form solution of the first-order loop is obtained and approximate solutions are derived for the second-order loops with RC, leadlag and perfect integrator filters. The perdormance of APLL's and their characteristics are also thoroughly investigated through experiments. In order to analyze the effect of the stochastic nature on nonlinear dynamics characteristics of the second order APLL, the phase error distribution and its variance have been obtained by using the Fokker-Planck equation. Theoretical results agree closely with those of experiment.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.2C
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• pp.191-200
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• 2002

A frequency synthesizer that can be used in IMT-2000 was designed and fabricated using dual loop PLL(Phase Locked Loop) in this paper. For improving phase noise characteristic two loops, reference loop and main loop, were divided. Phase noise was improved by transformed clamp type voltage controled oscillator and optimizing loop bandwidth in reference loop. And voltage controlled oscillator open loop gain in main loop. Fabricated the frequency synthesizer had 1.81GHz center frequency, 160MHz tuning range, 13.5dBm output power and -119.73dBc/Hz low phase noise characteristic.

• 한국ITS학회:학술대회논문집
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• 2005.11a
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• pp.209-214
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• 2005

• 한국ITS학회:학술대회논문집
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• 2004.11a
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• pp.186-191
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• 2004

• Journal of IKEEE
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• v.26 no.4
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• pp.714-721
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• 2022

A phase-locked loop (PLL)-based frequency synthesizer is proposed for a system on a chip (SoC) using multi-frequency clock signals. The proposed PLL-based frequency synthesizer consists of a charge pump PLL which is implemented by a phase frequency detector (PFD), a charge pump (CP), a loop filter, a voltage controlled oscillator (VCO), and a frequency divider, and an edge combiner. The PLL outputs a 12-phase clock by a VCO using six differential delay cells. The edge combiner synthesizes the frequency of the output clock through edge combining and frequency division of the 12-phase output clock of the PLL. The proposed PLL-based frequency synthesizer is designed using a 55-nm CMOS process with a 1.2-V supply voltage. It outputs three clocks with frequencies of 166 MHz, 83 MHz and 124.5MHz for a reference clock with a frequency of 20.75 MHz.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.15 no.6
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• pp.150-158
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• 2016

This paper is on a design of a new balise system which has a new functional part of a micro-power inductive wireless loop vehicle detector. The field test has processed and the data has analyzed for check the solar energy operable ability of the detect data interconnect sub-system which includes repeaters and field controllers. Instead of a railroad environment, 12 individual parking-lots are used for field test environment. As a result, in the condition of the designed system and the test environment, it is assumed that under 200 passing vehicles(train or tram) per day can be processed only with solar energy.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2002.11a
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• pp.394-397
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• 2002

A design study of phase detectors for the 2.5 Gb/s CDR circuit using a standard 0.18-${\mu}{\textrm}{m}$ CMOS process has been performed. The targeted CDR is based on the phase-locked loop and thus it consists of a phase detector, a charge pump, a LPF, and a VCO. For high frequency operation of 2.5 Gb/s, phase detector and charge pump, which accurately compare phase errors to reduce clock jitter, are critical for designing a reliable CDR circuit. As a phase detector, the Hogge phase detector is selected but two transistors are added to improve the performance of the D-F/F. The charge pump was also designed to be placed indirectly input and output.