• Journal of Multimedia Information System
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• 제5권2호
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• pp.131-138
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• 2018

This work describes a binary image based fast Difference of Gaussian (DoG) filter using zero-dimensional (0-d) convolution and state machine look up tables (LUTs) for image and video stitching hardware platforms. The proposed approach for using binary images to obtain DoG filtering can significantly reduce the data size compared to conventional gray scale based DoG filters, yet binary images still preserve the key features of the image such as contours, edges, and corners. Furthermore, the binary image based DoG filtering can be realized with zero-dimensional convolution and state machine LUTs which eliminates the major portion of the adder and multiplier blocks that are generally used in conventional DoG filter hardware engines. This enables fast computation time along with the data size reduction which can lead to compact and low power image and video stitching hardware blocks. The proposed DoG filter using binary images has been implemented with a FPGA (Altera DE2-115), and the results have been verified.

• 전기전자학회논문지
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• 제20권4호
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• pp.344-350
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• 2016

본 논문에서는 움직이는 영상에 대해 물리적인 회전이 발생하였을 때, 빠른 보정을 처리하기 위해 회전된 영상의 회전 각도를 고속으로 처리하기 위한 ECP (Extreme Contour Point) 알고리즘의 FPGA (Field Programmable Gate Array) 하드웨어 설계를 최적화하였고, XC7Z020 xc7z020-3clg400 FPGA 보드와 xilinx 14.2 툴을 사용하여 검증하였다. 잘 알려진 각도 산출 알고리즘인 CORDIC (Coordinate Rotation Digital Integrated Computation)과 비교하여 4ns의 유사한 동작 속도 안에서 CORDIC 대비 Registers는 108%, Look Up Tables (LUTs)는 91% 감소하는 등 하드웨어 비용이 우수함을 확인하였다.

• 한국음향학회지
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• 제37권4호
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• pp.215-222
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• 2018

본 논문은 실시간 혈관내초음파 영상을 위한 후단부 시스템 개발과 성능 평가 결과에 관한 것이다. 개발한 후단부 시스템은 로직 사용량과 메모리 사용량을 최소화할 수 있는 효율적인 LUTs (Look-up Tables)을 사용하여 외부 메모리 없이 하나의 FPGA (Field Programmable Gate Array)만으로 시스템을 구성함으로써 시스템의 저비용, 소형화, 경량화가 가능하도록 설계하였다. 구현한 후단부 시스템의 정확도는 FPGA의 출력값과 VHDL (VHSIC Hardware Description Language) 코드를 MATLAB 프로그램을 사용하여 동일하게 구현하여 얻은 결과를 비교함으로써 검증하였다. 토끼 동맥을 이용한 ex-vivo 실험을 통하여 개발한 후단부 시스템이 실시간 혈관내초음파 영상에 적합함을 확인하였다.

• 전자공학회논문지A
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• 제33A권11호
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• pp.140-151
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• 1996

In this study, we designed the routing structure and logic block of a SRAM cell-based FPGA with symmetrical-array architecture. The designed routing structure is composed of switch matrices, routing channels and I/O blocks, and the routing channels can be subdivided into single length channels, double length channels and global length channels. The interconnection between wires is made through SRAM cell-controlled pass transistors. To reduce the signal delay in pass transistors, we proposed a scheme raising the gate-control voltage to 7V. The designed SRAM cells have built-in shift register capability, so there is no need for separate shift registers. We designed SRAM cells in the LUTs(look-up tables) to enable the wirte operations to be performed synchronously with the clock for ease of system application. Each logic block (LFU) has four 4-input LUTs, flip-flops and other gates, and the LUTs can be used a sSRAM memory. The LFU also has a dedicated carry logic, so a 4-bit adder can be implemented in one LFU. We designed our FPGA using 0.6.mu.m CMOS technology, and simulation shows proper operation of a 4 bit counter at 100MHz.

• 대한원격탐사학회:학술대회논문집
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• 대한원격탐사학회 2005년도 Proceedings of ISRS 2005
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• pp.378-380
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• 2005

Remote sensing of atmospheric aerosol using MODIS satellite data has been proven to be very useful in global/regional scale aerosol monitoring. Due to their large spatial resolution of $10km^2$ MODIS aerosol optical thickness (AOT) data have limitations for local/urban scale aerosol monitoring applications. Modified Bremen Aerosol Retrieval (BAER) algorithm developed by von Hoyningen-Huene et al. (2003) and Lee et al. (2005) has been applied in this study to retrieve AOT in fe resolutions of $500m^2$ over Korea. Look up tables (LUTs) were constructed from the aerosol properties based on sun-photometer observation and radiation transfer model calculations. It was found that relative error between the satellite products and the ground observations was within about $15\%$. Resulting AOT products were correlated with surface PMIO concentration data. There was good correlation between MODIS AOT and surface PM concentration under certain atmospheric conditions, which supports the feasibility of using the high-resolution MODIS AOT for local and urban scale air quality monitoring

• 전자공학회논문지C
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• 제35C권2호
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• pp.56-64
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• 1998

Multi-layered perceptrons that are a nonlinear neural network model, have been widely used for various applications mainly thanks to good function approximation capability for nonlinear fuctions. However, for digital hardware implementation of the multi-layere perceptrons, the quantization scheme using "look-up tables (LUTs)" is commonly employed to handle nonlinear signmoid activation functions in the neworks, and thus requires large amount of storage to prevent unacceptable quantization errors. This paper is concerned with a new effective methodology for digital hardware implementation of multi-layered perceptrons, and proposes a "piecewise affine approximation" method in which input domain is divided into (small number of) sub-intervals and nonlinear sigmoid function is linearly approximated within each sub-interval. Using the proposed method, we develop an expression and an error backpropagation type learning algorithm for a multi-layered perceptron, and compare the performance with the quantization method through Monte Carlo simulations on XOR problems. Simulation results show that, in terms of learning convergece, the proposed method with a small number of sub-intervals significantly outperforms the quantization method with a very large storage requirement. We expect from these results that the proposed method can be utilized in digital system implementation to significantly reduce the storage requirement, quantization error, and learning time of the quantization method.quantization method.

• Journal of Information Display
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• 제9권1호
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• pp.1-5
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• 2008

Two new impulsive driving technologies for 120Hz liquid crystal display (LCD) panels are proposed to improve moving picture quality. One technology generates the dark frame using an adder and a shifter simply without using any look up tables (LUTs). It results in a cost effective impulsive scheme with motion picture quality comparable to that of high speed driving. The other is a backlight flashing method designed to avoid ghost images. The issue of ghost images caused by the slow response time of liquid crystal (LC) is solved by means of 120Hz overdriving and 120Hz backlight flashing. Using the perceived blur edge time (PBET) metric, measured moving picture response time (MPRT) values were 10.8ms and 4.4ms, respectively, while that of 120Hz high speed driving was 10.1ms.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권4호
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• pp.436-442
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• 2016

An electroencephalogram (EEG)-connectome processor to monitor and diagnose mental health is proposed. From 19-channel EEG signals, the proposed processor determines whether the mental state is healthy or unhealthy by extracting significant features from EEG signals and classifying them. Connectome approach is adopted for the best diagnosis accuracy, and synchronization likelihood (SL) is chosen as the connectome feature. Before computing SL, reconstruction optimizer (ReOpt) block compensates some parameters, resulting in improved accuracy. During SL calculation, a sparse matrix inscription (SMI) scheme is proposed to reduce the memory size to 1/24. From the calculated SL information, a small world feature extractor (SWFE) reduces the memory size to 1/29. Finally, using SLs or small word features, radial basis function (RBF) kernel-based support vector machine (SVM) diagnoses user's mental health condition. For RBF kernels, look-up-tables (LUTs) are used to replace the floating-point operations, decreasing the required operation by 54%. Consequently, The EEG-connectome processor improves the diagnosis accuracy from 89% to 95% in Alzheimer's disease case. The proposed processor occupies $3.8mm^2$ and consumes 1.71 mW with $0.18{\mu}m$ CMOS technology.

• 센서학회지
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• 제32권4호
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• pp.246-251
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• 2023

Internet of Things (IoT) systems process signals from various sensors using signal processing algorithms suitable for the signal characteristics. To analyze complex signals, these systems usually use signal processing algorithms in the frequency domain, such as fast Fourier transform (FFT), filtering, and short-time Fourier transform (STFT). In this study, we propose a multi-mode sensor signal processor (SSP) accelerator with an FFT-based hardware design. The FFT processor in the proposed SSP is designed with a radix-2 single-path delay feedback (R2SDF) pipeline architecture for high-speed operation. Moreover, based on this FFT processor, the proposed SSP can perform filtering and STFT operation. The proposed SSP is implemented on a field-programmable gate array (FPGA). By sharing the FFT processor for each algorithm, the required hardware resources are significantly reduced. The proposed SSP is implemented and verified on Xilinxh's Zynq Ultrascale+ MPSoC ZCU104 with 53,591 look-up tables (LUTs), 71,451 flip-flops (FFs), and 44 digital signal processors (DSPs). The FFT, filtering, and STFT algorithm implementations on the proposed SSP achieve 185x average acceleration.