• Journal of the Optical Society of Korea
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• v.9 no.3
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• pp.111-118
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• 2005

In this paper, a new optical parallel binary arithmetic processor (OPBAP) capable of computing arbitrary n-bit look-ahead carry full-addition is proposed and implemented. The conventional Boolean algebra is considered to implement OPBAP by using two schemes of optical logic processor. One is space-variant optical logic gate processor (SVOLGP), the other is shadow-casting optical logic array processor (SCOLAP). SVOLGP can process logical AND and OR operations different in space simultaneously by using free-space interconnection logic filters, while SCOLAP can perform any possible 16 Boolean logic function by using spatial instruction-control filter. A dual-rail encoding method is adopted because the complement of an input is needed in arithmetic process. Experiment on OPBAP for an 8-bit look-ahead carry full addition is performed. The experimental results have shown that the proposed OPBAP has a capability of optical look-ahead carry full-addition with high computing speed regardless of the data length.

• Journal of Korean Institute of Industrial Engineers
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• v.25 no.1
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• pp.35-46
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• 1999

The introduction of general purpose machining centers and the information system based on computer network has added a new control problem to the classical job shop control problems: a routing problem. A routing problem is to determine the machine on which a part will be processed. The modern manufacturing systems are given much system status information including the arrival time of the future parts via the computer network for automation. This paper presents and tests the performance of a routing procedure, LARP(Look-Ahead Routing Procedure) which uses look-ahead information on the future arrival of parts in the system. The manufacturing system considered in this paper has multi-stations which consists of general purpose machines and processes parts of different types. The application of LARP under many operating conditions shows that the reduction of part flow time and tardiness from the cases without using this information is up to 8% for flow time and 21% for tardiness. The procedure introduced here can be used for many highly automated systems such as an FMS and a semi-conductor fabrication system for routing where the arrivals of parts in the near future are known.

• The KIPS Transactions:PartA
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• v.15A no.5
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• pp.243-248
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• 2008

This paper proposes a low-power carry look-ahead adder using multi-threshold voltage CMOS. The designed adder is compared with conventional CMOS adder. The propagation delay time is reduced by using low-threshold voltage transistor in the critical path. Also, the power consumption is reduced by using high-threshold voltage transistor in the shortest path. The other logic block is implemented with normal-threshold transistor. Comparing with the conventional CMOS circuit, the proposed circuit is achieved to reduce the power consumption by 14.71% and the power-delay-product by 16.11%. This circuit is designed with Samsung $0.35{\mu}m$ CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2000.04a
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• pp.252-257
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• 2000

This paper describes a look-ahead algorithm of PCNC(personal computer numerical control). The algorithm is based on acceleration/deceleration before interpolation never including a command error and determines a velocity value in end point of each block(or start point of each block). The algorithm is represented as following; 1) calculating two maximum arrival velocity(v1, v2) by a acceleration value, a command velocity and distance in a previous block and a next block, 2) getting a tangent velocity(v3) of the adjacent blocks, 3) choosing a minimum value among these three velocities, and 4) setting the value to a velocity of a start point of the next block(or a end point of the previous block). The proposed look-ahead algorithm was implemented and tested by using a commercial RTOS(real time operation system) on the MS-Windows NT 4.0 in a PC platform. For interfacing to a machine, a counter board, a DAC board and a DIO board were used. The result of the algorithm increased a machining precision and a machining speed in many short blocks.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2006.05a
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• pp.457-458
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• 2006

A method for obtaining smooth, jerk bounded feed rate profile in high speed machining has been developed. This study proposes a NURBS interpolator based on adaptive feed rate control with a well developed look ahead algorithm which takes into account the machining dynamics as well. Limitation of jerk and proportional torque rate result in smoothened loads on the machine which effectively reduces excitation of the resonant frequencies of the machine. It is found that the values of the feed rate of the down stream sharp corner have profound effect on the feed rate of the upstream sharp corners. By using a windowing scheme the feed rate profile obtained after look ahead method is re-interpolated to reduce the jerk related problems. This is compared with the adaptive NURBS interpolator to show the effectiveness of the proposed method. Simulation results indicate that the consideration of 'ripple effect' is important in avoiding jerk and thereby increasing the machining accuracy.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.9 no.6
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• pp.71-81
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• 2000

This paper describers a look ahead algorithm of PC-NC(personal computer numerical control). The algorithm is based on acceleration/deceleration before interpolation which doesn\`t include a command error and determines a feedrate value at the end point of each block(or start point of each block). The algorithm is represented as following; 1) calculating two maximum arrival feedrates(F$_1$,F$_2$) by an acceleration value, a command feedrate, and the distance of a NC block, 2) getting a tangent feedrate (F$_3$) of the adjacent blocks, 3) choosing a minimum value among these three feedrates, and 4) setting the value to a feedrate of a start point of the next block(or a end point of the previous block). The proposed look ahead algorithm was implemented and tested by using a commercial TROS(real time operation system) on the MS-Windows NT 4.0 in a PC platform. For interfacing to a machine, a counter board, a DAC board and a DIO board were used. The result of the algorithm increased a machining precision and a machining speed in many short blocks.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.8
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• pp.34-41
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• 2002

This paper describes a scalable implementation method of a word-based RSA cryptoprocessor using pseudo carry look-ahead adder The basic organization of the modular multiplier consists of two layers of carry-save adders (CSA) and a reduced carry generation and Propagation scheme called the pseudo carry look-ahead adder for the high-speed final addition. The proposed modular multiplier does not need complicated shift and alignment blocks to generate the next word at each clock cycle. Therefore, the proposed architecture reduces the hardware resources and speeds up the modular computation. We implemented a single-chip 1024-bit RSA cryptoprocessor based on the word-based modular multiplier with 256 datapaths in 0.5${\mu}{\textrm}{m}$ SOG technology after verifying the proposed architectures using FPGA with PCI bus.

• Journal of IKEEE
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• v.22 no.4
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• pp.896-900
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• 2018

Traditionally, Linear Shift Feedback Register (LFSR) has been widely employed to implement Cyclic Redundant Check (CRC) codes for a serial input. Since many applications including network and storage systems demand as high throughput as ever, various efforts have been made to implement CRC hardware to support parallel inputs. Among various parallel schemes, the look-ahead scheme is one of the most widely used schemes due to its short critical path. However, it is very cumbersome to design HDL codes for parallel CRC codes since the look-ahead scheme is inevitable to consider how register and input values move in the next cycles. Thus, this paper proposes a novel CRC hardware generator, which automatically produces HDL codes given a CRC polynomial and parallel factor. The experimental results verify the applicability to use the proposed generator by analyzing the synthesis results from the generated HDL code.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 2004.05a
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• pp.433-436
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• 2004

반도체 및 LCD 제조 라인의 물류 제어 시스템을 위하여 시스템의 현재 및 미래의 Look ahead 정보를 사용하고 반송장비의 운반 상황을 동시에 고려하면서 디스패칭(dispatching) 과정을 수행하는 RTLAD(Real Time Look Ahead Dispatcher)를 위한 핵심 기법들을 개발한다. 특히, 베이(bay) 내에서 로트의 가공이 완료 되었을 때 다음 스텝 공정을 위하여 목적지 장비를 실시간으로 결정하는 절차를 제시하며, 동시에 목적지 장비까지의 반송장비를 선택하는 절차를 제시한다. 목적지 장비 결정 과정에서 반송장비의 상황을 함께 고려한다.

• Proceedings of the Korea Inteligent Information System Society Conference
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• 2006.06a
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• pp.311-315
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• 2006

Viterbi decoder는 크게 BM(Branch metric), ACS(Add-Compare-Select), SM(Survivor Memory) block 으로 구성되어 있다. 이중 ACSU 부분은 고속 데이터 처리를 위한 bottleneck이 되어 왔으며, 이의 해결을 위한 많은 연구가 활발히 진행되어 왔다. look ahead technique은 ACSU를 M-step으로 처리하고 CS(Carry save) number를 사용한 새로운 비교 알고리즘을 제안하여 high throughput을 추구했으며, minimized method는 block processing 방식으로 forward, backward 방향으로 decoding을 수행하여 ACSU 부분의 feedback을 완전히 제거하여 exteremely high throughput 을 추구하고 있다. 이에 대해 look ahead technique 의 기본 PE(Processing Element)를 바탕으로 minimized method 알고 리즘의 core block 을 bit-level 로 구현하였으며 : code converter 를 이용하여 CS number 가운데 redundat number(l)를 제거하여 비교기를 더 간단히 하였다. SYNOPSYS의 Design compiler 와 TSMC 0.18 um library 를 이용하여 합성하였다.