• Proceedings of the IEEK Conference
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• 2004.06a
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• pp.7-10
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• 2004

This paper describes techniques to implement low-cost adapt ive Pipelined LMS filter for ASIC implement ions of high communication receivers. Power consumpiton can be reduced using a careful selection of architectural, algorithmic, and VLSI circuit techlifue A Pipelined architecture for the strength-reduced algorithm is then developed via the relaxed look-ahead transformation. This technique, which is an approximation of the conventional look-ahead compution, maintains the functionality of the algorithm rather than the input-output behavior Convergence maiysis of the Proposed architecture has been presented and support via simulation results. The resulting pipelined adaptive filter achives a higher though put requires lower power as compared to the filter using the serial algorithm.

• Proceedings of the Acoustical Society of Korea Conference
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• 1998.06c
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• pp.75-78
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• 1998

이 논문에서는 대용량 연속음성 인식에서 인식 속도를 향상시키기 위한 방법들에 대해서 연구하였다. 음성인식에 있어서 많은 양의 계산을 요하는 부분은 관측 확률의 계산과 탐색에 필요한 계산이다. 탐색에 필요한 계산을 줄이기 위하여 빔 탐색법과 phoneme look-ahead기법을 통해 탐색 공간을 줄였으며, 관측 확률을 계산하는데 소요되는 시간을 줄이기 위하여 입력 특징 벡터와 이웃 관계에 있는 가우시안 성분들만 정확한 계산을 하는 VQ에 의한 계산량 감축 방법과 tree-structured pdf 방법을 구현하였다. 3천개의 어휘와 2천여개의 트라이폰 모델로 구성된 연속 음성인식 시스템에서 보통의 Viterbi 빔 탐색법을 적용한 경우에 실시간의 2.73배의 인식 속도로 93.39%의 단어 인식률을 얻을 수 있는데 phoneme look-ahead 기법과 tree-structured pdf 방법을 추가 적용함으로써 비슷한 인식 성능에서 1.55배의 인식 속도를 얻을 수 있었다.

• IE interfaces
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• v.17 no.spc
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• pp.131-140
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• 2004

The purpose of this paper is to develop and show the efficiency of the URL(Unload Request Logic) and LRL(Load Request Logic) of the dispatcher in the Fab(Fabrication) Manufacturing Execution System. These logics are the core procedures which control the material(wafer and glass substrate) flow efficiently in the semiconductor and LCD fab considering inter-bay as well as intra-bay material flow. We use the present and future status information of the system by look-ahead and the information about the future transportation schedule of Automated Guided Vehicles. The simulation results show that the URL and LRL presented in this paper reduce the average lead time, average and maximum WIP level, and the average available AGV waiting time.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2007.05a
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• pp.115-119
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• 2007

In this paper, practical problems will be covered in applying preview control to real tracked vehicle systems. Previous researches about the preview control assume that the vehicle speed is constant and the actuators have full frequency bandwidth. However, in order to apply it to real systems, those should be taken into account. Therefore this paper show the algorithm to apply the preview control to speed changing vehicles and performance variation according to a restricted frequency bandwidth.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 1994.04a
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• pp.280-287
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• 1994

본 논문에서는 광양제철소의 연속소둔공정의 작업단위편성 문제를 소개하고, 그 해결방안을 제시한다. 다루고자 하는 문제는 편성할 스케줄 내에서 전후 대상재간의 다양한 형태의 편차를 최소화하며 sequence의 길이를 최대화하 는 목적함수를 가지며, 동시에 공정의 특성상 발생하는 전후 대상재간의 제 약조건들을 만족시키는 문제이다. 이러한 문제를 해결하기 위하여 부분 최적 해를 구해 주는 순차적인 두가지 발견적(heuristic)기법을 제시한다. 첫째, 일 정의 길이를 최대화하며 전후 대상재간의 제약조건을 만족시키기 위한 "backtracking with look ahead" 기법이다. 특히 이 "backtracking with look ahead" 기법은 이미 개발된 "constraint satisfaction problem"을 기반으로 한 일정계획언어와 이에 연동된 코드생성기를 사용하여 구현되었다. 둘째, sequence내 전후 대상재간의 다양한 형태의 편차를 최소화하며 앞에서 만족 시킨 제약조건들을 계속 유지시키기 위한 평활화(smoothing) 기법이다. 마지 막으로 두가지 발견적 기법을 사용하여 본 연속소둔공정의 작업단위편성 문 제를 해결하는 과정을 보여준다. 이와 같은 발견적 기법을 이용하여 기존의 기법들로는 해결하기 힘든 복잡한 형태의 일정 계획 문제를 해결할 수 있었 다. 복잡한 형태의 일정 계획 문제를 해결할 수 있었 다.

• Proceedings of the KIEE Conference
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• 2000.11d
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• pp.794-796
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• 2000

This paper analyzes the method of cascading 74LS163 4-Bit Binary Counters. The 74LS163 4-Bit Binary Counter has synchronous LD. CLR functions and especially ENT, ENP, RCO to cascade some chips in order to count more 4bit binary number. The maximum operating frequency may vary according to the method of cascading. The Data sheet from Texas Instruments introduces two methods, The Ripple Carry Mode Circuit and The Carry Look Ahead Circuit, and shows that The Carry Look Ahead Circuit is more efficient than the other. However, there are only little information for user to understand and apply this to other circuits. Thus, we not only analyzed the two methods but also compared with each other in the point of performance.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.7
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• pp.37-45
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• 1998

A 32-b self-timed parallel carry look-ahead adder (PCLA) designed for 0.5.mum. single threshold low power CMOS technology is demonstrated to operate with 2.7nsec delay at 8mW under 1V power supply. Compared to static PCLA and DPL adder, the self-timed PCLA designed with NORA logic provides the best performance at the power consumption comparable to other adder structures. The wave pipelined clock control play a crucial role in achieving the low power, high performance of this adder by eliminating the unnecessary power consumption due to the short-circuit current during the precharge phase. Th enoise margin has been improved by adopting the physical design of staic CMOS logic structure with controlled transistor sizes.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.4
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• pp.240-245
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• 2006

Viterbi decoder is composed of BMU(Branch metric Unit), ACSU(Add Compare Select Unit), and SMU(Survivor path Memory Unit). For high speed viterbi decoders, ACSU is the main bottleneck due to the compare-select and feedback operation. Thus, many studies have been advanced to solve the problem. For example, M-step look ahead technique and Minimized method are typical high speed algorithms. In this paper, we designed a bit-level ACSU(K=3, R=1/2, 4bit soft decision) based on those algorithms and switched the matrix product order in the backward direction of Minimized method so as to apply Code-Optimized-Array in order to reduce the area complexity. For experimentation, we synthesized our design by using SYNOPSYS Design compiler, with TSMC 0.18 um library, and verified the timing by using CADENCE verilog-XL.

• Journal of the Korea Society of Computer and Information
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• v.4 no.3
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• pp.47-52
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• 1999

The efficiency of an adder which plays an important role in micro-process and DSP greatly depends on the kinds of carry generation method. So in this paper. I used both CLA excellent in the speed and CSA best in the chip-size. The 64bit adder is designed with high speed which is two optimum combination. Therefore this paper suggested the way of CLSA improving both speed and chip-size. and proved the excellence of the designed circuit.

• Journal of Korea Society of Industrial Information Systems
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• v.11 no.4
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• pp.32-39
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• 2006

MANET is a dynamically reconfigurable wireless network with no fixed infrastructure (base station, or AP). In order to provide the data service in MANET, we need an efficient routing protocol to deliver the data to the wanted destination at a mobile node. A method of routing protocols called reactive routing protocol has recently got attention because of their low routing overhead. But a method of flooding broadcasts the packet to all of its neighbors. For this reason, each of the node has high routing overhead to route and keep path discovery. Accordingly in this paper, I propose an adaptive flooding scheme using N-hop look-ahead in MANET, md an optimal N value of doing flooding the packet to limited area. Because of being basically ignorant about topological changes, each of the node did not spontaneously cope with path alteration. But an efficient flooding scheme applying N-hop look-ahead is more resilient to topology changes than traditional algorithms. And also with this efficient flooding scheme, the simulation results demonstrate excellent reduction of routing overhead.