• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.6
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• pp.37-43
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• 1999

Two-way addressing method has been proposed for efficient VLSI implementation of Euclidean calculation circuit for pipelined Reed-Solomon decoder. This new circuit is operating with single clock while exploiting maximum parallelism, and uses register addressing instead of register shifting to minimize the switching power. Logic synthesis shows the circuit with the new scheme takes 3,000 logic gates, which is about 40% reduction from the previous 5,000 gate implementation. Computer simulation also shows the power consumption is about 3mW. The previous implementation with multiple clock consumed about 5mW.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.13 no.1
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• pp.35-47
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• 2004

In this paper presents a new approach to the design and real-time implementation of fuzzy control system based-on digital signal processors(DSP:IMS320C80) in order to improve the precision and robustness for system of industrial robot(Dual-Arm with 8 joint Robot). The need to meet demanding control requirement in increasingly complex dynamical control systems under significant uncertainties, leads toward design of intelligent manipulation robots. The IMS320C80 is used in implementing real time fuzzy control to provide an enhanced motion control for robot manipulators. In this paper, a Self-Organizing Fuzzy Controller(SOFC) for the industrial robot manipulator with a actuator located at the base is studied. A fuzzy logic composed of linguistic conditional statements is employed by defining the relations of input-output variables of the controller. In the synthesis of a FLC(Fuzzy Logic Controller), one of the most difficult problems is the determination of linguistic control rules from the human operators. To overcome this difficult SOFC is proposed for a hierarchical control structure consisting of basic and high levels that modify control rules. The proposed SOFC scheme is simple in structure, Int in computation, and suitable for implementation of real-time control. Performance of the SOFC is illustrated by simulation and experimental results for a Dual-Arm robot with eight joints.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.35T no.1
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• pp.59-66
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• 1998

In this paper, the high-speed decoder for RS(Reed-Solomon) code, one of the most popular error correcting code, is implemented using VHDL. This RS decoder is designed in transform domain instead of most time domain. Because of the simplicity in structure, transform decoder can be easily realized VLSI chip. Additionally the pipeline architecture, which is similar to a systolic array is applied for all design. Therefore, This transform RS decoder is suitable for high-rate data transfer. After synthesis with FPGA technology, the decoding rate is more 43 Mbytes/s and the area is 1853 LCs(Logic Cells). To compare with other product with pipeline architecture, this result is admirable. Error correcting ability and pipeline performance is certified by computer simulation.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.2
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• pp.1-11
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• 1997

We developed a base station modulator ASIC for CDMA digital cellular system. In CDMA digital cellular system, the modulation is performed by convolutional encoding and QPSK with spread spectrum. The function blocks of base station modulator are CRC, convolutional encoder, interleaver pseudo-moise scrambler, power control bit puncturing, walsh cover, QPSK, gain controller, combiner and multiplexer. Each function block was designed by the logic synthesis of VHDL codes. The VHDL code was described at register transfer level and the size of code is about 8,000 lines. The circuit simulation and logic simulation were performed by COMPASS tools. The chip (ES-C2212B CMB) contains 25,205 gates and 3 Kbit SRAM, and its chip size is 5.25 mm * 5,45 mm in 0.8 mm CMOS cell-based design technology. It is packaged in 68 pin PLCC and the power dissipation at 10MHz is 300 mW at 5V. The ASIC has been fully tested and successfully working on the CDMA base station system.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.11
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• pp.4597-4603
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• 2010

A factorization is a very important part of multi-level logic synthesis. The number of literals in a factored form is an estimate of the complexity of a logic function, and can be translated directly into the number of transistors required for implementation. Factored forms are described as either algebraic or Boolean, according to the trade-off between run-time and optimization. A Boolean factored form contains fewer number of literals than an algebraic factored form. In this paper, we present a new method for a Boolean factorization. The key idea is to identify two-cube nonkernel Boolean pairs from given expression. Experimental results on various benchmark circuits show the improvements in literal counts over previous other factorization methods.

• Journal of the Korean Institute of Intelligent Systems
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• v.15 no.5
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• pp.527-532
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• 2005

In this paper, we proposed an adaptive fuzzy sliding control for unknown nonlinear systems using estimation of bounds for approximation errors. Unknown nonlinearity of a system is approximated by the fuzzy logic system with a set of IF-THEN rules whose consequence parameters are adjusted on-line according to adaptive algorithms for the purpose of controlling the output of the nonlinear system to track a desired output. Also, using assumption that the approximation errors satisfy certain bounding conditions, we proposed the estimation algorithms of approximation errors by Lyapunov synthesis methods. The overall control system guarantees that the tracking error asymptotically converges to zero and that all signals involved in controller are uniformly bounded. The good performance of the proposed adaptive fuzzy sliding mode controller is verified through computer simulations on an inverted pendulum system.

• Journal of Internet Computing and Services
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• v.25 no.1
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• pp.29-37
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• 2024

In this paper, we propose an efficient image processing system to detect and track the movement of specific objects such as patients. The proposed system extracts the outline area of an object from a binarized difference image by applying a thinning algorithm that enables more precise detection compared to previous algorithms and is advantageous for mixed-mode design. The binarization and thinning steps, which require a lot of computation, are designed based on RTL (Register Transfer Level) and replaced with optimized hardware blocks through logic circuit synthesis. The designed binarization and thinning block was synthesized into a logic circuit using the standard 180n CMOS library and its operation was verified through simulation. To compare software-based performance, performance analysis of binary and thinning operations was also performed by applying sample images with 640 × 360 resolution in a 32-bit FPGA embedded system environment. As a result of verification, it was confirmed that the mixed-mode design can improve the processing speed by 93.8% in the binary and thinning stages compared to the previous software-only processing speed. The proposed mixed-mode system for object recognition is expected to be able to efficiently monitor patient movements even in an edge computing environment where artificial intelligence networks are not applied.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11A
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• pp.936-944
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• 2003

In this paper, we propose an AND/XOR-based technology mapping method for field programmable gate arrays (FPGAs). Due to the fixed size of the programmable blocks in an FPGA, decomposing a circuit into sub-circuits with appropriate number of inputs can achieve excellent implementation efficiency. Specifically, the proposed technology mapping method is based on Davio expansion theorem to decompose a given Boolean circuit. The AND/XOR nature of the proposed method allows it to operate on XOR intensive circuits, such as error detecting/correcting, data encryption/decryption, and arithmetic circuits, efficiently. We conduct experiments using MCNC benchmark circuits. When using the proposed approach, the number of CLBs (configurable logic blocks) is reduced by 67.6% (compared to speed-optimized results) and 57.7% (compared to area-optimized results), total equivalent gate counts are reduced by 65.5 %, maximum combinational path delay is reduced by 56.7 %, and maximum net delay is reduced by 80.5 % compared to conventional methods.

• Journal of Satellite, Information and Communications
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• v.12 no.4
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• pp.62-66
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• 2017

In this paper, we present the development of communication and data processing strategy for the electromagnetic wave precipitation gauge system. The electromagnetic wave precipitation gauge system is a small system for deriving area rainfall rates within 1 km radius through dual polarization radar observation at 24GHz band. It is necessary to take consider for measurement of accurate precipitation under limited computing resources originating from small systems and to minimize the use of network for the unattended operation and remote management. To overcome computational resource limitations, we adopted the fuzzy logic for quality control to eliminate non-precipitation echoes and developed the method by weighted synthesis of various rain rate fields using multiple radar QPE formulas. Also we have designed variable data packets rules to minimize the network traffic.

• The Journal of Korean Association of Computer Education
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• v.20 no.4
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• pp.77-84
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• 2017

This paper proposes a tool that can be used as a logical expression simplification tool that can be used for deepening learning of logic circuits and further utilized as a design automation tool for optimizing semiconductor parts. The simplification method of logical expressions proposed in this paper is to find common subexpressions existing in various logical expressions and reduce the repetitive use. Finally, the goal is to minimize the number of literals used in all logical expressions. These previous studies failed to produce a common subexpression embedded in the logical expressions because they only use division principle. The proposed method uses cubes with a Hamming distance of 3 to find the common subexpression embedded between logical expressions. Experiments using benchmark circuits show that the proposed method reduces the number of literals by as much as 47% when comparing simplifications with other methods.