• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.377-380
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• 2001

In this paper, we propose new partial product compressor and ENMODL (Enhanced-NORA-MODL) CLA(Carry Look-ahead Adder) for high speed and low power multiplier. To reduce transistor count, area, power we developed two new-approaches. One is small size partial product compressor, the other is dynamic CMOS logic ENMODL CLA. The transistor count of new compressor is reduced by 11% as compared with that of conventional one. The speed of ENMODL CLA is increased by 6.27% as compared with NMODL CLA.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.925-928
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• 1999

A multi-channel gas leakage monitoring system was designed and fabricated by using CPLD(complex Programmable Logic .Device) for monitoring and controlling the leakage of natural gas from supplying-pipes under the ground. Fabricated SnO$_2$thick film gas sensor elements were attached on safeguard steel plate of natural gas supplying pipes, and the local monitoring system in this study received the signal from the gas sensors. The monitoring system was implemented by using CPLD chip to reduce the development time and implement simple one chip system. The time division multi-channel system received the input signal from individual gas sensor at one of divided times by multiplexor and signal processed sequentially. The system reduced the size of peripheral circuit resulted in implementation of creditable simple system.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.356-359
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• 1999

A high performance 16bit multiplier for asynchronous systems has been designed using asynchronous design methodology. The 4-radix modified Booth algorithm, TSPC (true single phase clocking) registers, and modified 4-2 counters using DPTL (differential pass transistor logic) have been used in our multiplier. It is implemented in 0.65${\mu}{\textrm}{m}$ double-poly/double-metal CMOS technology by using 6616 transistors with core size of 1.4$\times$1.1$\textrm{mm}^2$. And our design results in a computation rate exceeding 60MHz at a supply voltage of 3.3V.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.25 no.4
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• pp.40-45
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• 2002

An AS/RS construction cost minimization model under throughput rate requirement constraint has been developed, whose objective function includes S/R machine cost, storage rack cost, and interrace conveyor cost. S/R machine cost is a function of the storage rack height, the unit load weight, and the control logic used by the system, while storage rack cost is a function of the storage rack height, the weight and the volume of the unit load. Since the model is a nonlinear integer programming problem which is very hard to solve exactly with large problem size, a solution procedure is developed to determine the height and the length of the storage rack with a fixed number of S/R machines, while increasing the number of S/R machines one by one to meet the throughput rate requirement.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.8
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• pp.22-38
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• 1997

This paper proposes a new VLSI architecture for morphological filters and presents its chip design and implementation. The proposed architecture can significantly reduce hardware costs compared with existing architecture by using a feedback loop path to reuse partial results and a decoder/encoder pair to detect maximum/minimum values. In addition, the proposed architecture requires one common architecture for both diltion and erosion and fewer number of operations. Moreover, it can be easily extended for larger size morphologica operations. We developed VHDL (VHSIC hardware description language) models, performed logic synthesis using the SYNOPSYS CAD tool. We used the SOG (sea-of-gate) cell library and implemented the actual chip. The total number of gates is only 2,667 and the clock frequency is 30 MHz that meets real-time image processing requirements.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.52 no.10
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• pp.575-582
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• 2003

A new FDOs (fault diagnostic observers) and the residual generation schemes using the FDOs are suggested for the process fault detection and isolation of linear (control) systems. The design method of the FDO is described, first, for the full measurement systems. Then it is extended for the systems with unmeasurable state variables. An unknown input observer is proposed and applied for the extension. The size of the observer bank may be the smallest, specially in full measurement systems, because the order of the proposed FDO is very low. In spite of the simplicity, the scheme provides the same information for the detection and isolation of the anticipated faults as the conventional multiple observer based schemes. The residuals may be structured so that fault isolation can be performed by pre-selected logic. An FDIS using the proposed scheme is constructed for the model of the four-tank system. Simulation results show the practical feasibility of the proposed scheme.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.4 no.2
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• pp.205-210
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• 2004

This paper deals with rule extraction from data using rough set theory. We construct the rule base in a hierarchical granulation structure by applying core as a classification criteria at each level. When more than one core exist, the coverage is used for the selection of an appropriate one among them to increase the classification rate and accuracy. In Addition, a probabilistic approach is suggested so that the partially useful information included in inconsistent data can be contributed to knowledge reduction in order to decrease the effect of the uncertainty or vagueness of data. As a result, the proposed method yields more proper and efficient rule base in compatability and size. The simulation result shows that it gives a good performance in spite of very simple rules and short conditionals.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.10 no.2
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• pp.95-100
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• 2010

This paper proposes a new spatial regularization of Fisher linear discriminant analysis (LDA) to reduce the overfitting due to small size sample (SSS) problem in face recognition. Many regularized LDAs have been proposed to alleviate the overfitting by regularizing an estimate of the within-class scatter matrix. Spatial regularization methods have been suggested that make the discriminant vectors spatially smooth, leading to mitigation of the overfitting. As a generalized version of the spatially regularized LDA, the proposed regularized LDA utilizes the non-uniformity of spatial correlation structures in face images in adding a spatial smoothness constraint into an LDA framework. The region-dependent spatial regularization is advantageous for capturing the non-flat spatial correlation structure within face image as well as obtaining a spatially smooth projection of LDA. Experimental results on public face databases such as ORL and CMU PIE show that the proposed regularized LDA performs well especially when the number of training images per individual is quite small, compared with other regularized LDAs.

• Nuclear Engineering and Technology
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• v.29 no.6
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• pp.433-443
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• 1997

In this work, an analytic approach to the dependability of software in the operational phase is suggested with special attention to the hardware fault effects on the software behavior : The hardware faults considered are memory faults and the dependability measure in question is the reliability. The model is based on the simple reliability theory and the graph theory which represents the software with graph composed of nodes and arcs. Through proper transformation, the graph can be reduced to a simple two-node graph and the software reliability is derived from this graph. Using this model, we predict the reliability of an application software in the digital system (ILS) in the nuclear power plant and show the sensitivity of the software reliability to the major physical parameters which affect the software failure in the normal operation phase. We also found that the effects of the hardware faults on the software failure should be considered for predicting the software dependability accurately in operation phase, especially for the software which is executed frequently. This modeling method is particularly attractive for the medium size programs such as the microprocessor-based nuclear safety logic program.

• Proceedings of the KSR Conference
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• 1998.05a
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• pp.408-418
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• 1998

This paper presents the implementation of comparator which is self-testing with respect to the faults caused by any single physical defect likely to occur in NMOS and CMOS integrated circuit. The goal is to use it for the fault-tolerant system. First, a new fault model for PLA(Programmable Logic Array) is presented. This model reflects several physical defects in VLSI circuits. It focuses on the designs based on PLA because VLSI chips are far too complex to allow detailed analysis of all the possible physical defects that can occur and of the effects on the operation of the circuit. Second, this paper shows that these design, which has been implemented with 2 level AND-ORor NOR-NOR circuit, are optimal in term of size. And it also presents a formal proof that a comparator implemented using NOR-NOR PLA, based on these design, is sol f-testing with respect to most single faults in the presented fault model. Finally, it discusses the application of the self-testing comparator as a building block for the implementation of the fault-tolerant system.