• JSTS:Journal of Semiconductor Technology and Science
• /
• v.13 no.2
• /
• pp.157-169
• /
• 2013

Scale Invariant Feature Transform (SIFT) generates image features widely used to match objects in different images. Previous work on hardware-based SIFT implementation requires excessive internal memory and hardware logic [1]. In this paper, a new hardware organization is proposed to implement SIFT with less memory and hardware cost than the previous work. To this end, a parallel Gaussian filter bank is adopted to eliminate the buffers that store intermediate results because parallel operations allow all intermediate results available at the same time. Furthermore, the processing order is changed from the raster-scan order to the block-by-block order so that the line buffer size storing the source image is also reduced. These techniques trade the reduction of memory size with a slight increase of the execution time and external memory bandwidth. As a result, the memory size is reduced by 94.4%. The proposed hardware for SIFT implementation includes the Descriptor generation block, which is omitted in the previous work [1]. The addition of the hardwired descriptor generation improves the computation speed by about 30 times when compared with the previous work.

• School Mathematics
• /
• v.12 no.1
• /
• pp.45-60
• /
• 2010

In school mathematics, gakdo(korean, ie angular measure in english) lost effectiveness as a term, on the other hand, an expression gak-ui-kugi(korean, ie size of angle in english) is prevalent these days. So it is necessary to accept this expression. It is necessary to specify in textbook that the size of angle rely on the degree of gap between two edges regardless of the length of edges. The content of curriculum manual and the content of textbooks must be reconciled. Random units for measuring the size of angle are not contained in textbooks. It can be possible, but it is not carried out actually. So, it is necessary not to require it in curriculum manual considering this circumstance. In curriculum manual, it is necessary to specify the role of 1-right angle as a standard unit, and situations to use it must be presented in textbooks. In cut-paste method of finding the sum of the size of three angles in a triangle and the sum of the size of four angles in a quadrilateral, keeping a straight angle and one rotation in mind, an explanation is based upon a premise that students know how to express the $180{^{\circ}}$ and $360{^{\circ}}$ in figure as a result. It is a leap of logic.

• Health Policy and Management
• /
• v.10 no.4
• /
• pp.99-115
• /
• 2000

This study was conducted to get a resonable set of budget allocation to public health programs. Matrix Delphi technique was used to obtain the logic of study results and eventually to form a human model which could predict opinion of professionals on budget allocation. Thirty-two professionals in academic and governmental area responded to Delphi survey. Questionnaire was developed using matrix formation, and the matrix was formed by 6 decision criteria on budget allocation and 26 public health programs. The decision criteria are as following: size of problem(morbidity), severity of problem, social equity, importance of prevention, technical feasibility and efficiency of programs. Severity of problem dropped out of the model because it had significant correlation with the size of problem. A total score of each program was obtained by weighting the relative importance of each criteria which also were given by survey respondents. These total scores indicate that the most important public health program is vaccination for infants and children in terms of budget allocation. Monitoring communicable diseases, mental health program, and anti-smoking program are the next. In addition, respondents were asked of the desirable budget size of each program. The result was rearranged by multiple regression model using the scores of each decision criteria. In this process, the current budget size of central government was provided to the respondents, and included in the model. h set of desirable budgets modified using tile model was obtained. Considering the current size of budget, tile results of the model is very different from that of the total score. Managing dementia is ranked the first. Health promotion program for the elderly, rehabilitation of the disabled and monitoring communicable diseases are the next. The need to increase the budget of vaccination for the infants and children was not found as so high. The matrix structure in Delphi survey gave us the precise basis to make optimal decision, and made it possible to develop an opinion predicting model. However the plentifulness and diversity of professional opinions were not fully obtained due to the limited number of decision criteria.

• Journal of the Korean Institute of Telematics and Electronics D
• /
• v.36D no.1
• /
• pp.47-56
• /
• 1999

As the density of logic gates of VLSI chips has rapidly increased, more number of I/O pins has been required. This results in bigger package size and higher packager cost. The package cost is higher than the cost of bare chips for high I/O count VLSI chips. As the density of logic gates increases, the reduction method of the number of I/O pins for a given complexity of logic gates is required. In this paper, we propose the novel I/O interface circuit using CTR (Constant-Transition-Rate) code to reduce 50% of the number of I/O pins. The rising and falling edges of the symbol pulse of CTR codes contain 2-bit digital data, respectively. Since each symbol of the proposed CTR codes contains 4-bit digital data, the symbol rate can be reduced by the factor of 2 compared with the conventional I/O interface circuit. Also, the simultaneous switching noise(SSN) can be reduced because the transition rate is constant and the transition point of the symbols is widely distributed. The channel encoder is implemented only logic circuits and the circuit of the channel decoder is designed using the over-sampling method. The proper operation of the designed I/O interface circuit was verified using. HSPICE simulation with 0.6 m CMOS SPICE parameters. The simulation results indicate that the data transmission rate of the proposed circuit using 0.6 m CMOS technology is more than 200 Mbps/pin. We implemented the proposed circuit using Altera's FPGA and confimed the operation with the data transfer rate of 22.5 Mbps/pin.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.5
• /
• pp.83-93
• /
• 2013

Recently, the SURF algorithm, which is conjugated for object tracking system as part of many computer vision applications, is a well-known scale- and rotation-invariant feature detection algorithm. The SURF, due to its high computational complexity, there is essential to develop a hardware accelerator in order to be used on an IP in embedded environment. However, the SURF requires a huge local memory, causing many problems that increase the chip size and decrease the value of IP in ASIC and SoC system design. In this paper, we proposed a way to design a SURF algorithm in hardware with greatly reduced local memory by partitioning the algorithms into several Sub-IPs using external memory and a DMA. To justify validity of the proposed method, we developed an example of simplified object tracking algorithm. The execution speed of the hardware IP was about 31 frame/sec, the logic size was about 74Kgate in the 30nm technology with 81Kbytes local memory in the embedded system platform consisting of ARM Cortex-M0 processor, AMBA bus(AHB-lite and APB), DMA and a SDRAM controller. Hence, it can be used to the hardware IP of SoC Chip. If the image processing algorithm akin to SURF is applied to the method proposed in this paper, it is expected that it can implement an efficient hardware design for target application.

• Journal of Korea Water Resources Association
• /
• v.43 no.3
• /
• pp.275-282
• /
• 2010

The purpose of culvert design is to determine optimum size for a safe drainage of flood discharge. The present method of culvert design in Korea is generally carried out by using "Road Drainage Design" of Korea Expressway Corporation (1991), which is based on the manual of Federal Highway Association (FHWA) of USA. However, this method may result in subjective error because of using graphs and the usage of nomograph can be a major obstacle for computer modelling. Some errors found in the previous works of culvert design are corrected, and a new logic has been developed for a simple determination of culvert size in this study. FHWA (1985) presents a nomograph to determine the critical water depth and the velocity head for a circular pipe, but in this study simple explicit equations have been developed to determine both respectively.

• The KSFM Journal of Fluid Machinery
• /
• v.19 no.6
• /
• pp.26-33
• /
• 2016

Combined heat and power (CHP) system is one of the power generation system which can generate both electricity and heat. Generally, mid-size and big-size CHP plant in Korea generate electricity from gas turbine and steam turbine, then supply heat from exhaust gas. Actually, CHP can supply heat using district heater which is located at low pressure turbine exit or inlet. When the district heater locates after low pressure turbine, which called back pressure type turbine, there need neither condenser nor mode change operating control logic. When the district heater locates in front of low pressure turbine or uses low pressure turbine extraction steam flow, which calls condensing type turbine, which kind of turbine requires condenser. In this case, mode change operation methods are used for generating maximum electricity or maximum heat according to demanding the seasonal electricity and heat.

• Journal of the Korea Computer Industry Society
• /
• v.2 no.2
• /
• pp.211-218
• /
• 2001

In this paper, we propose the structure of utilizing the memory map, which is using not conventional DRAM but SDRAM, for the hardware implementation of frame memory interface module to the video encoder. As reducing the size of memory map and interface buffer within the same bus, the hardware complexity is improved and the hardware size is minimized as simplifying the interface logic. The conventional system is wasted access time, because of accessing randomly stored data in order to store and output the memories in macro-block unit. therefore the method, which is proposed in this paper, can be effectively reducing the access time of memory, because of the data is stored and processed by line unit.

• Journal of the Korean Institute of Intelligent Systems
• /
• v.11 no.2
• /
• pp.178-183
• /
• 2001

Welding is essential for the manufacture of a range of engineering components which may vary from very large structures such as ships and bridges to very complex structures such as aircraft engines, or miniature components for microelectronic applications. Especially, a domestic situation of the welding automation is still depend on the arc sensing system in comparison to the vision sensing system. Specially, the gap-detecting of workpiece using conventional arc sensor is proposed in this study. As a same principle, a welding current varies with the size of a welding gap. This study introduce to the fuzzy membership filter to cancel a high frequency noise of welding current, and ART2 which has the competitive learning network classifies the signal patterns the filtered welding signal. A welding current possesses a specific pattern according to the existence or the size of a welding gap. These specific patterns result in different classification in comparison with an occasion for no welding gap. The patterns in each case of 1mm, 2mm, 3mm and no welding gap are identified by the artificial neural network.

• The KIPS Transactions:PartA
• /
• v.8A no.1
• /
• pp.48-55
• /
• 2001

Using BDD, we can represent Boolean functions uniquely and compactly, Hence, BDD have become widely used for CAD applications, such as logic synthesis, formal verification, and etc. The size of the BDD representation for a function is very sensitive to the choice of orderings on the input variables. Therefore, it is very important to find a good variable ordering which minimize the size of the BDD. Since finding an optimal ordering is NP-complete, several heuristic algorithms have been proposed to find good variable orderings. In this paper, we propose a variable ordering algorithm based on the $\mu$O(microcanonical optimization). $\mu$O consists of two distinct procedures that are alternately applied : Initialization and Sampling. The initialization phase is to executes a fast local search, the sampling phase leaves the local optimum obtained in the previous initialization while remaining close to that area of search space. The proposed algorithm has been experimented on well known benchmark circuits and shows superior performance compared to a algorithm based on simulated annealing.