• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1998년도 제13차 학술회의논문집
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• pp.205-209
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• 1998

A synthesis of fuzzy variable structure control is proposed to design a high-angle-of-attack flight system for a modification version of the F-18 aircraft. The knowledge of the proportional, integral, and derivative control is combined into the fuzzy control that addresses both the highly nonlinear aerodynamic characteristics of elevators and the control limit of thrust vectoring nozzles. A simple gain scheduling method with multi-layered fuzzy rules is adopted to obtain an appropriate blend of elevator and thrust vectoring commands in the wide operating range. Improving the computational efficiency, an accelerated kernel for on-line fuzzy reasoning is also proposed. The resulting control system achieves the good flying quantities during a high-angle-of- attack excursion. Thus the fuzzy logic can afford the control engineer a flexible means of deriving effective control laws in the nonlinear flight regime.

• 전자공학회논문지C
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• 제34C권6호
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• pp.22-27
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• 1997

This paper propose a novel VLSI architecture for a multiplierless FIR filter chip providing variable-length taps. To change the number of taps, we propose two special features called a data-reuse structure and a recurrent-coefficient scheme. These features consist of several MUXs and registers and reduce the number of gates over 20% compared with existing chips using an address generation unit and a modulo unit. Since multipliers occupy large VLSI area, a multiplierless filter chip meeting real-time requirement can save large area. We propose a modified bit-serial multiplication algorithm to compute two partial products in parallel, and thus, the proposed filter is twice faster and has smaller hardware than previous multiplierless filters. We developed VHDL models and performed logic synthesis using the 0.8.mu.m SOG (sea-of-gate) cell library. The chip has only 9,507 gates, was fabricated, and is running at 77MHz.

• 대한전기학회논문지:시스템및제어부문D
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• 제53권2호
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• pp.86-93
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• 2004

The DCT algorithm needs an efficient hardware architecture to compute inner product. The conventional design method, like ROM-based DA(Distributed Arithmetic), has large hardware complexity. Because of this reason, a CSHM(Computation Sharing Multiplication) was proposed for implementing inner product by Park. However, the Park's CSHM has inefficient hardware architecture in the precomputer and select units. Therefore it degrades the performance of the multiplier. In this paper, we presents the optimization design method for inner product using CSHM algorithm and applied it to implementation of 1-D DCT processor. The experimental results show that the proposed multiplier is more efficient than Park's when hardware architectures and logic synthesis results were compared. The designed 1-D DCT processor by using proposed design method is more high performance than typical methods.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 G
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• pp.3199-3201
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• 1999

Convolutional coding with Viterbi decoding is known as a powerful method for forward error correction among many kinds of channel coding methods. This paper presents a soft decision Viterbi decoder which has systolic array trace-back architecture[1]. Soft decision is known as more effective method than hard decision and most of digital communication systems use soft decision. The advantage of using a systolic array decoder is that the trace-back operation can be accomplished continuously in an array of registers in a pipe-line fashion, instead of waiting for the entire trace-back procedure to be completed at each iteration. Therefore it may be suitable for faster communication system. We described operations of each module of the decoder and showed results of the logic synthesis and functional simulation.

• 한국전기전자재료학회논문지
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• 제15권4호
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• pp.349-355
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• 2002

The ionic conductivity of cubic solid solutions in the systems of CaO-$ZrO_2$, $Y_2O_3-ZrO_2$ prepared by SHS was examined. The higher conductivity appears to be related to a lower activation energy rather than to the number of oxygen vacancies dictated by composition. Conductivity-temperature data was obtained at 1000 $^{\circ}C$ in atmosphere of low oxygen partial pressure (~$10^{-40}$ atm) for $Y_2O_3-ZrO_2$ cubic solid solutions. The data indicated that these materials could be reduced, and the decree of reduction would be related with the measuring electric field.

• Nuclear Engineering and Technology
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• 제48권2호
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• pp.470-481
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• 2016

Field-programmable gate arrays (FPGAs) have received much attention from the nuclear industry as an alternative platform to programmable logic controllers for digital instrumentation and control. The software aspect of FPGA development consists of several steps of synthesis and refinement, and also requires verification activities, such as simulations that are performed individually at each step. This study proposed an integrated software-testing framework for simulating all artifacts of the FPGA software development simultaneously and evaluating whether all artifacts work correctly using common oracle programs. This method also generates a massive number of meaningful simulation scenarios that reflect reactor shutdown logics. The experiment, which was performed on two FPGA software implementations, showed that it can dramatically save both time and costs.

• 한국정밀공학회지
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• 제25권6호
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• pp.62-70
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• 2008

An adaptive fuzzy backstepping controller is proposed for the motion control for a single-link flexible-joint robot in the presence of parametric uncertainties. Fuzzy logic system is used to approximate the uncertainties of functions and a backstepping technique is employed to deal with the mismatched problem. A compensation controller is also employed to estimates the bound of approximation error so that the shattering effect of the control effort can be reduced. Thus the asymptotic stability of the closed loop control system can be obtained based on a Lyapunov synthesis approach. Numerical simulation results for a single-link flexible-joint robot are included to show the effectiveness of proposed controller.

• 한국멀티미디어학회논문지
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• 제11권6호
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• pp.816-827
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• 2008

In this paper, two-stage pipelined floating-point arithmetic unit (FP-AU) is designed. The FP-AU processor supports seventeen operations to apply 3D graphics processor and has area-efficient and low-latency architecture that makes use of modified dual-path computation scheme, new normalization circuit, and modified compound adder based on flagged prefix adder. The FP-AU has about 4-ns delay time at logic synthesis condition using $0.18{\mu}m$ CMOS standard cell library and consists of about 5,930 gates. Because it has 250 MFLOPS execution rate and supports saturated arithmetic including a number of graphics-oriented operations, it is applicable to mobile 3D graphics accelerator efficiently.

• 대한전자공학회논문지SD
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• 제41권5호
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• pp.153-160
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• 2004

본 논문에서는 IEEE 802.11a 무선 LAN 시스템의 성능 향상과 전송율 증가를 위해 효율적인 비트 로딩 알고리즘 적용 방안을 제안하였다. 기존의 비트 로딩 알고리즘은 각 부채널의 신호대 잡음비(SNR)를 입력받아 수행되는데, 무선 LAN 시스템은 랜덤한 백색잡음 때문에 정확한 SNR 추정이 어렵다. 이는 비트 로딩을 적용할 때 이상적인 성능 이득보다 저하되는 문제점이 있다. 따라서 이 문제점을 해결하기 위해 SNR이 아닌 채널의 주파수 응답을 이용하는 비트 로딩 알고리즘을 제안하였다 모의 실험을 통해 기존의 비트 로딩 알고리즘을 무선 LAN 시스템에 적용하였을 때 PER이 10-2에서 전송 모드에 따라 0.5∼5㏈ 의 성능 이득을 얻은 반면, 제안된 방법의 비트 로딩 알고리즘은 동일한 조건에서 3.5 ∼8㏈ 사이의 성능 이득을 얻을 수 있었고, 데이터 전송율은 최대 54Mbps에서 63Mbps로 증가시킬 수 있음을 확인하였다. 또한 하드웨어 설계 결과, 제안된 방법을 적용한 비트 로딩 연산 블록은 4.2K의 gate count와 2.8Kbit 메모리를 포함하고, 기존의 비트 로딩 알고리즘보다 약 34%정도 감소함을 확인하였다.

• 한국통신학회논문지
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• 제24권6B호
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• pp.1183-1190
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• 1999

본 논문에서는 MPEG-2 비디오 인코더를 ASIC 칩으로 구현할 때, 움직임추정기와 함께 대량의 하드웨어 영역을 차지하는 프레임메모리 인터페이스를 개선한 효율적인 구조를 제시한다. 이를 위해 비디오 인코더와 듀얼 뱅크를 가지는 외부 SDRAM 사이의 인터페이스를 효율적으로 처리할 수 있도록 메모리 맵을 구성하고 메모리 액세스 타이밍을 최적화하여 내부 메모리 크기와 인터페이스 로직을 줄였다. 본 설계에는 0.5 m, CMOS, TLM(Triple Layer Metal) 표준 셀 라이브러리가 사용되었으며, 하드웨어 설계 및 검증을 위해서 VHDL 시뮬레이터와 로직 합성툴이 사용되었고, 기능 검증을 위한 테스트 벡터 생성을 위해서, C 언어로 모델링한 하드웨어 에뮬레이터가 사용되었다. 개선된 프레임 메모리 인터페이스의 구조는 기존의 구조[2-3]에 비해 58% 정도의 면적이 감소했으며, 전체 비디오 인코더에 대해서는 24.3% 정도의 하드웨어 면적이 감소되어, 프레임메모리 인터페이스가 비디오 인코더 전체의 하드웨어 면적에 대단히 심각한 영향을 미친다는 것을 결과로 제시한다.