• Journal of the Institute of Convergence Signal Processing
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• v.6 no.3
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• pp.134-142
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• 2005

The implementation of Multiple-Valued Logic(MVL) based on Current-Mode CMOS Logic(CMCL) circuits has recently been achieved. In this paper, four-valued Unary Multiple-Valued logic functions are synthesized using current-mode CMOS logic circuits. We properly make use of the fact that the CMCL addition of logic values represented using discrete current values can be performed at no cost and that negative logic values are readily available via reversing the direction of current flow. A synthesis process for CMCL circuits is based upon a logically complete set of basic elements. Proposed algorithm results in less expensive realization than those achieved using existing techniques in terms of the number of transistors needed. As an alternative to the cost-table techniques Universal Unary Programmable Circuit (UUPC) for a unary function is also proposed.

• Journal of the Korea Society of Computer and Information
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• v.4 no.4
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• pp.1-8
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• 1999

In the logic where we study the principle and method of human, the binary logic with the proposition which has one-valued property that it can be assigned the truth value 'truth'or 'false'. Although most of the traditional binary logic which was drawn by human includes fuzziness hard to deal with, the knowledge for expressing it is not precise and has less degree of credit. This study uses multi-valued logic in order to slove the problem above that .When compared with the data processing ability of the binary logic, Multi-valued logic has an at a high speed. Therefore the Inference can be possible by minimization multi-valued logic in stead of using the information stead of using the information system based on the symbolic binary logic.

• Journal of the Korean Solar Energy Society
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• v.32 no.4
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• pp.96-102
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• 2012

The minimum airflow of VAV terminal boxes is a key factor for comfort, indoor air quality(IAQ) and energy cost. If the minimum airflow is not reasonable, it would waste energy and make IAQ problems. There are two types of VAV terminal box control logic. One is the single maximum, another is the dual maximum control logic. Dual maximum control logic is more efficiency way to reduce the energy consumption. It has a minimum airflow set point and a heating maximum set point. It allows the minimum airflow set point to be much lower than single maximum control logic. A building simulation was conducted to evaluate the energy consumption and the IAQ according to the control logic of the V AV terminal box. In the simulation, dual maximum control logic can save the energy up to 6.5% compared to the single maximum control logic.

• Journal of Institute of Control, Robotics and Systems
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• v.6 no.1
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• pp.104-111
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• 2000

A fuzzy logic Run-by-Run(RbR) controller and an in -line wafer characteristics prediction scheme for the rapid thermal processing system have been developed for the study of process repeatability. The fuzzy logic RbR controller provides a framework for controlling a process which is subject to disturbances such as shifts and drifts as a normal part of its operation. The fuzzy logic RbR controller combines the advantages of both fuzzy logic and feedback control. It has two components : fuzzy logic diagnostic system and model modification system. At first, a neural network model is constructed with the I/O data collected during the designed experiments. The wafer state after each run is assessed by the fuzzy logic diagnostic system with featuring step. The model modification system updates the existing neural network process model in case of process shift or drift, and then select a new recipe based on the updated model using genetic algorithm. After this procedure, wafer characteristics are predicted from the in-line wafer characteristics prediction model with principal component analysis. The fuzzy logic RbR controller has been applied to the control of Titanium SALICIDE process. After completing all of the above, it follows that: 1) the fuzzy logic RbR controller can compensate the process draft, and 2) the in-line wafer characteristics prediction scheme can reduce the measurement cost and time.

• Journal of Practical Engineering Education
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• v.9 no.1
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• pp.41-48
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• 2017

In this paper, we proposed a method for digital logic circuit control, through arduino device programming with digital outputs, to design a curriculum for basic digital logic circuit practices. Curricula for arduino device programming and digital logic circuit are essentially practiced in engineering departments of colleges or high schools in South Korea. However, actual practice course lacks the experimental examples of digital logic circuit combined with arduino device programming. Furthermore, actual practice course lacks the curriculum in that students design and test their own digital logic circuits with the less cost than the oscilloscope. Therefore, to solve these problems in this paper, we proposed a curriculum for basic digital logic circuit practices during one semester. In this curriculum, students control and experiment their own digital logic circuits through arduino device programming with digital outputs.

• Journal of the Daesoon Academy of Sciences
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• v.20
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• pp.95-123
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• 2009

This paper is designed to show the relationship between the Daesoon Principle and the recent theories like transpersonal psychology(TP) and predicate logic. According to TP there are 3 categories and 8 elements inside of not only human consciousness but civilization; three are pre-ego, ego, trans-ego, and eight are Uroboros, Typhon, Greater Mother, solarization, and repetition of the previous fours. The former is called, for Ken Wilber, the Average mode and the latter, the Advanced mode. I think that Daesoon thought including general Korean National religions belongs to the Advanced mode. I applied the predicate logic or paradoxical logic to understand of the Harmony of God and Man as well as Correspondence of Yin with Yang. The paradoxical logic has been not acceptable through two thousands years in the western tradition. I call the paradoxical logic the E type logic in this paper. The E type logic is most suitable logic for apprehending the Daesoon philosophy to a large extent. Finally my paper may contribute to the globalization of Daesoon mind system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.1-7
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• 2008

Magnetic Tunneling Junction (MTJ) has been used as a nonvolatile universal storage element mainly in memory technology. However, according to several recent studies, magneto-logic using MTJ elements show much potential in substitution for the transistor-based logic device. Magneto-logic based on MTJ can maintain the data during the power-off mode, since an MTJ element can store the result data in itself. Moreover, just by changing input signals, the full logic functions can be realized. Because of its programmability, it can embody the reconfigurable magneto-logic circuit in the rigid physical architecture. In this paper, we propose a novel 3-bit arbitrary magneto-logic circuit beyond the simple combinational logic or the short sequential one. We design the 3-bit magneto-logic which has the most complexity using MTJ elements and verify its functionality. The simulation results are presented with the HSPICE macro-model of MTJ that we have developed in our previous work. This novel magneto-logic based on MTJ can realize the most complex logic function. What is more, 3-bit arbitrary logic operations can be implemented by changing gate signals of the current drivel circuit.

• Proceedings of the KIEE Conference
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• 2000.11d
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• pp.781-783
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• 2000

1bit full adder have 3 input (including carry_in) and 2 outputs(Sum and Carry_out). Because of 1 bit full adder's propagation delay. We usually use 4-bit binary full adder with fast carry, 74LS283. The 74LS283 is positive logic circuit chip. But the logic function of binary adder is symmetrical, so it can be possible to use it not only positive logic but also the negative logic. This thesis use symmetrical property. such as $C_{i+1}(\bar{a_i}\bar{b_i}\bar{c_i})=C_{i+1}{\bar}(a_i,\;b_i,\;c_i)$ and $S_i(\bar{a_i}\bar{b_i}\bar{c_i})=\bar{S_i}(a_i,\;b_i,\;c_i)$. And prove this property with logic operation. Using these property, the 74LS283 adder is possile as the negation logic circuit. It's very useful to use the chip in negative logic. because many system chip is negative logic circuit. for example when we have negative logic chip with 74LS283. we don't need any not gate for 74LS283 input, and just use output of adder(74LS283) as the negation of original output.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.4
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• pp.816-823
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• 2005

Non-Horn logic programs are extended from Horn logic programs to the level of 1st order predicate logic. Even though they are more expressive than Horn logic programs, They are not practically used because we do not have efficient implementations. Currently to execute non-Horn logic programs, we translate them to equivalent Horn logic programs using the proof procedure InH-Prolog and compile the Horn logic programs to WAM(Warren Abstract Machine) instructions. In this paper, we propose EWAM(Extended Warren Machine) that executes non-Horn logic programs more efficiently and a compilation scheme that compiles non-Horn logic programs to the EWAM instruction. We implement an EWAM emulator and a compiler and measured the performance of the EWAM emulator and the compiler and found that they are very efficient.

• Journal of Korea Society of Industrial Information Systems
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• v.16 no.5
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• pp.9-19
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• 2011

In many instances a concise form of logic is often required for building today's complex systems. The method described in this paper can be used for a wide range of industrial applications that requires Boolean type of logic minimization. Unlike some of the previous logic minimization methods, the proposed method can be used to better gain insights into the logic minimization process. Based on the decimal valued matrix, the method described here can be used to find an exact minimized solution for a given Boolean function. It is a visual based method that primarily relies on grouping the cell values within the matrix. At the same time, the method is systematic to the extent that it can also be computerized. Constructing the matrix to visualize a logic minimization problem should be relatively easy for the most part, particularly if the computer-generated graphs are accompanied.