• Journal of the Korean Society for Nondestructive Testing
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• v.31 no.2
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• pp.144-149
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• 2011

The lock-in thermography was employed to evaluate the integrity of railway bogies. Prior to the actual application on railway bogies, in order to assess the detectability of known flaws, the calibration reference panel was prepared with various dimensions of artificial flaws. The panel was composed of structural steel, which was the same material with actual bogies. Through lock-in thermography evaluation, the optimal frequency of heat source was determined for the best flaw detection. Based on the defects information, the actual defect assessments on railway bogie were conducted with different types of railway bogies, which were used for the current operation. In summary, the defect assessment results with thermography method showed a good agreement as compared with the conventional inspection techniques. Moreover, it was found that the novel infrared thermography technique could be an effective way for the inspection and the detection of surface defects on bogies since the infrared thermography method provided rapid and non-contact mode for the investigation of railway bogies.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.583-586
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• 2004

In this paper, we have analyzed the performance of synchronization of CCK(Complementary Code Keying) modulation scheme used for IEEE 802.11g wireless LAM system supporting 54 Mbps of high speed data rate over 2.4 GHz. At receiver, the clock frequency offset is caused by noise or fading. This frequency error occurs the offset of clock timing and causes ISI. Therefore the tracking is required to reduce the clock timing offset. The DLL(Delay Lock Loop), asychronization mode, performing tacking the clock is used for the simulation. The simulation result shows jitter variance and BER performance in the AWGN and multipath fading channel environment.

• The Journal of the Korea institute of electronic communication sciences
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• v.4 no.4
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• pp.247-252
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• 2009

This paper presents an Integer-N phase-locked loop (PLL) frequency synthesizer using a novel prescaler based on a charge pump and clock triggering circuit. A quadrature VCO has been designed for the 900MHz UHF RFID application. In this circuit, a voltage-controlled oscillator(VCO), a novel Prescaler, phase frequency detector(PFD), charge pump(CP), and analog lock detector(ALD) have been integrated with 0.35-${\mu}m$CMOS process. The integer divider has been developed with a verilog-HDL module, and the PLL mixed mode simulation has been performed with Spectre-Verilog co-simulator. The sweep range of VCO is designed from 828 to 960 MHz and the VCO generates four phase quadrature signals. The simulation results show that the phase noise of VCO is -102dBc/Hz at 100 KHz offset frequency, and the maximum lock-in time is about 4us with 32MHz step change (from 896 to 928 MHz).

• Transactions of the Korean Society of Automotive Engineers
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• v.4 no.4
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• pp.156-163
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• 1996

The brakes are the most important safety-critical accident avoidance components of a motor vehicle. They must perform safely under a variety of operating conditions and must have enough strength not to fail during the life of a vehicle. Recently, anti-lock brake systems are used on more and more passenger cars. The ABS brakes modulate brake line pressure to prevent brakes from locking during braking. In this study, finite element analysis, material test for FCD45, measurement of stress and cumulative fatigue damage analysis were performed to evaluate fatigue damage of the caliper housing under ABS mode.

• Journal of Institute of Control, Robotics and Systems
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• v.22 no.9
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• pp.759-765
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• 2016

This paper presents the principle, dynamics modeling and control, hardware implementation, and flight test result of a hybrid-type unmanned aerial vehicle (UAV). The proposed UAV was designed to provide both hovering and fixed-wing type aerodynamic flight modes. The UAV's flight mode transition was achieved through the attitude transformation in pitch axis, which avoids a complex rotor tilt mechanism from a structural and control viewpoint. To achieve this, a different navigation coordinate was introduced that avoids the gimbal lock in pitch singularity point. Attitude and guidance control algorithms were developed for the flight control system. For flight test purposes, a quadrotor attached with a tailless fixed-wing structure was manufactured. An onboard flight control computer was designed to realize the navigation and control algorithms and the UAV's performance was verified through the outdoor flight tests.

• Journal of Auto-vehicle Safety Association
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• v.5 no.1
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• pp.16-24
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• 2013

Some GM (General Motors) vehicles are using a GMLAN (General Motors Local Area Network) communication protocol for control and diagnostics. The airbag control module uses vehicle speed information from the GMLAN to record the vehicle speed as pre-crash information. In order to use the vehicle speed information for crash reconstruction purposes, it helps to be able to understand the accuracy of the data. The actual vehicle speed is not expected to be the same as the GMLAN indicated speed in some situations like a spin or if there is hard braking. This paper compares the actual vehicle speed and vehicle speed information during specific vehicle maneuvers. Actual vehicle speed is calculated from a GPS sensor, while GMLAN vehicle speed is calculated from transmission output sensor by the Engine control module (ECM). Vehicle maneuvers defined as Mode #1, Mode #2, Mode #3. The Mode #1 maneuver simulates wheel lock-up and skidding f by hard-braking at a specific speed. The Mode #2 maneuver simulates a 90degree turn using a J-turn maneuver at a specific speed. The Mode#3 maneuver simulates a 180 degree turn using a spin type of maneuver at a specific speed. The study then compares the GMLAN speed and GPS speed to see what speed difference exists between them. The results of this paper are applicable to GM vehicles only. This paper catalogs the performance and limitations of two vehicles as useful reference for crash reconstructions where there is a need to understand the speed indicated in the pre-crash section of the SDM data.

• International Journal of Automotive Technology
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• v.8 no.2
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• pp.211-217
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• 2007

The wheel slip control systems are able to control the braking force more accurately and can be adapted to different vehicles more easily than conventional ABS (Anti-lock Brake System) systems. In realizing the wheel slip control systems, real-time information such as the tire braking force at each wheel is required. In addition, the optimal target slip values need to be determined depending on the braking objectives such as minimum braking distance and stability enhancement. In this paper, a robust wheel slip controller is developed based on the adaptive sliding mode control method and an optimal target slip assignment algorithm is proposed for maximizing the braking force. An adaptive law is formulated to estimate the braking force in real-time. The wheel slip controller is designed based on the Lyapunov stability theory considering the error bounds in estimating the braking force and the brake disk-pad friction coefficient. The target slip assignment algorithm searches for the optimal target slip value based on the estimated braking force. The performance of the proposed wheel slip control system is verified in HILS (Hardware-In-the-Loop Simulator) experiments and demonstrates the effectiveness of the wheel slip control in various road conditions.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.23-30
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• 2005

This paper describes a DLL(delay locked loop)-based multi-clock generator having the lower active stand-by power as well as a fast relocking after re-activating the DLL. for low power and high speed VLSI chip. It enables a frequency multiplication using frequency multiplier scheme and produces output clocks with 50:50 duty-ratio regardless of the duty-ratio of system clock. Also, digital control scheme using DAC enables a fast relocking operation after exiting a standby-mode of the clock system which was obtained by storing analog locking information as digital codes in a register block. Also, for a clock multiplication, it has a feed-forward duty correction scheme using multiphase and phase mixing corrects a duty-error of system clock without requiring additional time. In this paper, the proposed DLL-based multi-clock generator can provides a synchronous clock to an external clock for I/O data communications and multiple clocks of slow and high speed operations for various IPs. The proposed DLL-based multi-clock generator was designed by the area of $1796{\mu}m\times654{\mu}m$ using $0.35-{\mu}m$ CMOS process and has $75MHz\~550MHz$ lock-range and maximum multiplication frequency of 800 MHz below 20psec static skew at 2.3v supply voltage.

• Transactions of the Korean Society for Noise and Vibration Engineering
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• v.20 no.10
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• pp.976-982
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• 2010

This paper proposes a novel type of pressure control mechanism which can apply to vehicle ABS (anti-lock braking system) utilizing the piezoactuator based valve system associated with the pressure modulator. As a first step, a flapper-nozzle of a pneumatic valve system is devised by integrating the piezoacuator to the flexible beam structure. The dynamic modeling of the valve system is then undertaken and subsequently the governing equation of pressure control is derived considering the pressure modulator. A sliding mode controller is designed in order to achieve accurate pressure tracking control in the presence of actuator uncertainty as well as input pressure variation. It is shown through computer simulation that an accurate pressure tracking for sinusoidal motion whose magnitude is 40 bar is achieved by utilizing the proposed pressure control mechanism.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.963-964
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• 2006

By combining a digital DLL and an analog DLL in 2-stage, an improved DLL is implemented in this paper. The proposed DLL is composed of a RDLL (Register Controlled DLL) and a conventional analog DLL. The phase comparator used in the DLL is built with sense-amp based D flip-flops for high speed operation. The proposed DLL circuits have been designed, simulated in 0.18um, 1.8V TSMC CMOS library. The implemented DLL have demonstrated the fast lock-on time of 1us and low jitter of 72ps.