• 한국정밀공학회지
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• 제19권1호
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• pp.99-106
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• 2002

For the development of a ultra-precision CNC polishing system including on-machine measurement system, we study a corrective polishing algorithm. We calculated unit removal profiles for various flat type polishing tools and polishing tool positions. Using these results we simulate the corrective polishing process based on dwell time control. We calculate dwell time distributions and residual error of the polishing simulation method and the FFT calculation method. We test corrective polishing algorithm with an optical glass. The target removal shape is a sine wave that has amplitude 0.3 micro meters. We find this polishing process has a machining resolution of nanometer order and is effective for sub-micrometer order machining. This result will be used for the software development of the CNC polishing system.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2001년도 춘계학술대회 논문집
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• pp.950-955
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• 2001

For the development of an ultra-precision CNC polishing system including on-machine measurement system, we study a corrective polishing algorithm. We analyze and test the unit removal profiles for a ball type polishing tool. Using these results we calculate dwell time distributions and residual errors for a target removal shape. We use the polishing simulation method and feed rate calculation method for the dwell time calculation. We test corrective polishing algorithm with an optical glass. The target removal shape is a sine wave that has amplitude 0.3 micro meters. We find this polishing process has a machining resolution of nanometer order and is effective for sub-micrometer order machining. This result will be used for the software development of the CNC polishing system.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2000년도 추계학술대회 논문집
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• pp.783-786
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• 2000

For the development of a ultra-precision CMC polishing system including on-machine measurement system, we study a corrective polishing algorithm. We calculated unit removal profiles for various polishing tools and polishing tool positions. Using these results we simulate the corrective polishing process based on dwell time control. We calculate dwell time distributions and residual error of the polishing simulation method and the FFT calculation method. We got good dwell time distributions and small residual when we used the FFT calculation method. This results will be used for the optimization of corrective polishing process.

• 한국전기전자재료학회논문지
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• 제14권1호
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• pp.1-5
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• 2001

STI(shallow trench isolation)-CMP(chemical mechanical polishing) process have been substituted for LOCOS(local oxidation of silicon) process to obtain global planarization in the below sub-0.5㎛ technology. However TI-CMP process, especially TI-CMP with RIE(reactive ion etching) etch back process, has some kinds of defect like nitride residue, torn oxide defect, etc. In this paper, we studied how to reduced torn oxide defects after STI-CMP with RIE etch back processed. Although torn oxide defects which can occur on trench area is not deep and not severe, torn oxide defects on moat area is not deep and not severe, torn oxide defects on moat area is sometimes very deep and makes the yield loss. Thus, we did test on pattern wafers which go through trench process, APECVD process, and RIE etch back process by using an IPEC 472 polisher, IC1000/SUVA4 PAD and KOH base slurry to reduce the number of torn defects and to study what is the origin of torn oxide defects.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.525-526
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• 2007

Over-polishing is required to completely remove the material of top surface across whole wafer, in spite of a local dishing problem. This paper introduces the two-step CMP process using protective layer and high selectivity slurry, to reduce dishing amount and variation. The 30nm thick protective oxide layer was deposited on the pattern, and then polished with low selectivity slurry to partially remove the projected area while suppressing the removal rate of the recessed area. After the first step CMP process, high selectivity slurry was used to minimize the dishing amount and variation in pattern structure. Experimental result shows that two-step CMP process can be successfully applicable to reduce the dishing defect generated in over-polishing.

• 한국산학기술학회논문지
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• 제15권9호
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• pp.5460-5466
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• 2014

본 연구에서는 실생활에 많이 이용되며 주로 주방용 식기 및 식칼, 소형칼, 주방 가위 등으로 널리 사용되는 STS420J2를 실험소재로 사용하였다. 마르텐사이트계 스테인리스강은 Cr13%이상 함유하고 있어 약 $1,050^{\circ}C$를 정점으로 하여 그 이상의 고온에서는 저하하는 단점을 가지고 있다. 실험에 사용되는 시험편 표면에 표면경화를 수행하기 위하여 #200 ~ #1500의 순서대로 미세연마 후 거친연마 가공을 실시하였으며, 다이오드 레이저의 표면경화 열처리 후에 자기냉각효과를 고려하여 $100{\times}50{\times}10$의 판재로 시험편을 제작하여 실험하였다. 소재 표면에 다이오드 레이저를 이용하여 국소부위에 표면경화 열처리를 수행하였다. 이때 다이오드 레이저의 출력과 이송속도를 공정조건으로 하여, 미세경도시험, 미세조직시험, 전자 주사 현미경(SEM), 입열량을 분석하였다. 분석 후에는 실험소재의 기계적 특성을 비교하여, 타 표면경화법에 비해 다이오드 레이저를 이용하였을 때의 표면경화 열처리 신뢰성과 우수함 그리고 최적의 공정조건을 도출하였다. 열처리 후 경화부는 Plate martensite로 경화 되었으며. 경도값은 Hv606.2로 열처리 후 약 3배 이상 표면경도가 향상되었다.