• Journal of Power Electronics
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• 제18권4호
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• pp.997-1006
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• 2018

This paper proposes a transformerless photovoltaic (PV) power converter system based on the DC/AC boost inverter, which can solve the leakage current and second-order ripple power issues in single-phase grid-connected PV inverters. In the proposed topology, the leakage current can be decreased remarkably since most of the common-mode currents flow through the output capacitor, by-passing parasitic capacitors, and grounding resistors. In addition, the inherent ripple power component in the single-phase grid inverter can be suppressed without adding any extra components. Therefore, bulky electrolytic capacitors can be replaced by small film capacitors. The effectiveness of the proposed topology has been verified by simulation and experimental results for a 1-kW PV PCS.

• 전력전자학회:학술대회논문집
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• 전력전자학회 1999년도 전력전자학술대회 논문집
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• pp.373-376
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• 1999

This paper propose a "common mode voltage damper" that is capable of reducing the common mode voltage produced in the PWM VSI. An push-pull circuits and high frequency leakage current damper[1] are incorporated into the "common mode voltage damper", the design method of which is presented. Effect of "common mode voltage damper" is simulated in this paper verifies the viability and effectiveness in 2.2kW induction motor drive using IGBT inverter. Simulated results show that "common mode voltage damper" makes significant contributions to reducing a high frequency leakage current.ducing a high frequency leakage current.

• ETRI Journal
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• 제30권4호
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• pp.624-626
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• 2008

Excessively high temperature deteriorates the reliability and increases the leakage power consumption of microprocessors. The register file, known as one of the hottest functional units in microprocessors, incurs frequent dynamic thermal management operations for thermal control. In this letter, we adopt the banked register file scheme, which was originally proposed to reduce dynamic power consumption. By simply modifying the register file structure, the temperature in the register file was reduced dramatically, resulting in 13.37% performance improvement and 10.49% total processor leakage reduction.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권4호
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• pp.240-248
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• 2009

Moore's law has driven silicon technology scale down aggressively, and it results in significant increase of leakage current on nano-meter scale CMOS. Especially, in mobile devices, leakage current has been one of designers' main concerns, and thus many studies have introduced low power methodologies. However, there are few studies to minimize implementation cost in the mixed use of the methodologies to the best of our knowledge. In this paper, we introduce industrial applications of low power design methodologies for the decrease of leakage current. We focus on the design cost reduction of power gating and reverse body bias when used together. Also, we present voltage scale as an alternative to reverse body bias. To sustain gate leakage current, we discuss the adoption of high-$\kappa$ metal gate, which cuts gate leakage current by a factor of 10 in 32 nm CMOS technology. A 45 nm mobile SoC is shown as the case study of the mixed use of low power methodologies.

• IEIE Transactions on Smart Processing and Computing
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• 제1권2호
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• pp.117-124
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• 2012

A client collaboration (CC) system is proposed for a user relay system. The proposed scheme focuses on the management of transmit power and leakage interference. In the proposed CC system, edge users transmit signals to the masters considered as user relays. The masters relay the signals of the edge users to the base station using the resource blocks (RBs) that are assigned to the edge users. The leakage interference and power consumption were analyzed in the CC system. In addition, an optimal master location problem was formulated based on the signal-to-leakage-plus-noise ratio (SLNR). Because the optimal master location problem is quite complex, a sub-optimal master location problem was proposed and a closed-form sub-optimal master location was obtained. The edge users generate smaller leakage interference and power consumption in the proposed CC system compared to the system without the CC. The numerical results showed that the edge users generate smaller leakage interference and power consumption in the proposed CC system compared to the system without the CC, and the average throughput increases.

• 대한기계학회논문집B
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• 제23권9호
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• pp.1106-1112
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• 1999

Substantial losses behind axial flow rotor are generated by the wake, various vortices in the hub region and the tip leakage vortex in the tip region. Particularly, the leakage vortex formed near blade tip is one of the main causes of the reduction of performance, generation of noise and aerodynamic vibration in downstream. In this study, the three-dimensional flow fields in an axial flow rotor were calculated with varying tip clearance under various flow rates, and the numerical results were compared with experimental ones. The numerical technique was based on SIMPLE algorithm using standard $k-{\varepsilon}$ model(WFM) and Launder & Sharma's Low Reynolds Number $k-{\varepsilon}$ model(LRN). Through calculations, the effects of tip clearance and attack angle on the 3-dimensional flow fileds behind a rotor and leakage flow/vortex were investigated. The presence of tip leakage vortex, loci of vortex center and its behavior behind the rotor for various tip clearances and attack angles was described well by calculation.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권1호
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• pp.11-19
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• 2007

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit which becomes more serious problem due to the thin gate oxide and small threshold voltage in nanometer CMOS technology and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm predictive CMOS technology and uses a 0.9V power supply voltage. The simulation results show that the proposed PLL achieves a 88% jitter reduction at 440MHz output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of $40M{\sim}725MHz$ with a multiplication range of 11023, and the RMS and peak-to-peak jitter are 5ps and 42.7ps, respectively.

• 한국수자원학회:학술대회논문집
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• 한국수자원학회 2009년도 학술발표회 초록집
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• pp.260-266
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• 2009

본 연구는 지방상수도 배급수 관망의 유수율을 향상시키기 위하여 수량관리를 위한 블록시스템 구축을 통한 구역화 계량, 누수의 정량화를 위한 야간최소유량 측정을 통한 누수평가지표 및 국제 누수지수ILI(Infrastructure Leakage Index)의 도입, 압력제어를 통한 누수저감 효과분석, 장기적인 계획수립을 위하여 노후수도관의 잔존수명 예측 등 누수를 평가 관리할 수 있는 기술을 개발, 제안하였다. N시 야간최소유량 측정을 통하여 주거지역과 상업지역에서 정량적인 누수평가지표로 관길이당, 급수전당의 허용기준누수량을 산정하였다. 이는 관망정비가 완료된 주거, 상업지역을 각각 대상으로 UK water industry에서 제안한 방법을 이용하여 실측을 통한 야간최소유량을 분석함으로써 유수율을 대신할 수 있는 허용누수량 산정식을 개발하였다. 압력제어를 통한 누수저감효과는 감압변의 설치를 통하여 수행되는데, 사천시 우티 배수구역을 대상으로 압력관리 구역을 4개로 분할하고 감압밸브 3개소, 가압펌프 1개소를 설치하여 압력을 조절한 결과 약 $466\;m^3/day$의 누수를 저감시킬 수 있을 것으로 나타나 압력관리를 통하여 연간 113백만의 비용절감효과가 기대되었다. 노후 상수관로의 부식속도 및 잔존수명 예측 연구에서는 매설년도, 토양 또는 수질특성에 따른 관체의 부식속도를 평가함으로써 잔존두께를 예측할 수 있는 모델을 개발하였으며 또한 부식으로 인한 공식특성에 따른 잔존강도 등을 평가할 수 있는 비선형회귀 모형을 개발, 수도관의 잔존수명예측에 활용하여 장단기 노후관 개대체 계획수립에 활용할 수 있도록 제안하였다. 본 연구의 결과들은 지방상수도의 유수율 제고 및 관망정비사업에 적극적으로 활용할 수 있는 누수평가 및 관리기법을 제안할 수 있을 것으로 기대된다.

• 한국추진공학회:학술대회논문집
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• 한국추진공학회 2005년도 제24회 춘계학술대회논문집
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• pp.23-26
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• 2005

LOx와 Kerosene을 연료로 사용하는 LRE(Liquid Rocket Engine) Block에서 지상연소시험을 수행할 경우에 발생하는 위험도를 감소시키는 방법을 연구하였다. 추진제누출로 이어지는 위험한 상황에 대한 원인분석도와 추진제 유출시 사고로 이어지는 발전 양상 및 발전 프로세스, 사고시 손실을 줄이기 위한 기술적인 해결방법을 제시함으로써 기존의 확률적인 통계 값을 바탕으로 하는 것과는 또 다른 방법으로써 위험을 감소하기 위한 대안으로 사용하고자 한다.

• Journal of Mechanical Science and Technology
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• 제18권6호
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• pp.979-989
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• 2004

Numerical simulations have been performed to investigate tip clearance effect on through-flow and performance of a centrifugal compressor which has the same configuration of impeller with six different tip clearances. Secondary flow and loss distribution have been surveyed to understand the flow mechanism due to the tip clearance. Tip leakage flow strongly interacts with mainstream flow and considerably changes the secondary flow and the loss distribution inside the impeller passage. A method has been described to quantitatively estimate the tip clearance effect on the performance drop and the efficiency drop. The tip clearance has caused specific work reduction and additional entropy generation. The former, which is called inviscid loss, is independent of any internal loss and the latter, which is called viscous loss, is dependent on every loss in the flow passage. Two components equally affected the performance drop as the tip clearances were small, while the efficiency drop was influenced by the viscous component alone. The additional entropy generation was modeled with all the kinetic energy of the tip leakage flow. Therefore, the present paper can provide how to quantitatively estimate the tip clearance effect on the performance and efficiency.