• Transactions on Electrical and Electronic Materials
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• 제1권3호
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• pp.23-28
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• 2000

A block-oxide layer was formed on the surface of Cu-based leadframe by chamical oxidation method in order to enhance the adhesion strength between Cu-based leadframe and epoxy molding compound (EMC) Using sandwiched double cantilever beam (SDCB) specimens, the adesion strength was measured in terms of interfacial fracture toughness, G$\sub$IC//Results showed that the black-oxide layer was composed of two kinds of layers: pebble-like Cu$_2$O layer and acicular CuO layer, At the initial stage of oxidation the Cu$_2$O layer was preferentially formed and thickened up to around 200 nm whithin 1 minute of the oxidation time. Then the CuO layer started to from atop of the Cu$_2$O layer and thickened up to around 1300 nm until 20 minutes. As soon as the CuO layer formed, the thickness of Cu$_2$O layer began to reduce and finally reached to around 150 nm. The pre-cleaned and the Cu$_2$O coated leadframes showed almost no adhesion of EMC, however, as the CuO precipitates appeared and became continuous, G$\sub$IC/ increased up to around 80 J/㎡. Further oxidation raised G$\sub$IC/ up. to around 100 J/㎡.

• 한국공작기계학회논문집
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• 제17권3호
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• pp.14-19
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• 2008

In the semiconductor IC(Integrated Circuit) package, the top surface of silicon chip is directly attached to the area of the leadframe with a double-sided adhesive layer, in which the base layer have the upper adhesive layer and the lower adhesive layer. The IC package structure has been known to encounter a thermo-mechanical failure mode such as delamination. This failure mode is due to the residual stress on the adhesive surface of silicon chip and leadframe in the curing-cooling process. The induced thermal stress in the curing process has an influence on the cooling residual stress on the silicon chip and leadframe. In this paper, for the minimization of the chip surface damage, the adhesive topologies on the silicon chip are studied through the finite element analysis(FEA).

• 한국전산구조공학회논문집
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• 제13권1호
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• pp.97-103
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• 2000

이 논문에서는, 반도체 칩과 리드프레임을 결합하는 과정에서 점탄성 접착제층에 발생하는 잔류응력 문제를 다루고 있다. 접착제층은 “열유동단순”거동을 한다고 가정하였다. 접착제층에서의 응력들은 경계요소법을 사용하여 조사하였다. 매우 큰 응력 구배가 계면 모서리에서 발생하는데, 그러한 응력들은 국부 항복을 일으키거나, 칩과 리드프레임의 박리를 야기시킬 수 있음을 보여주고 있다.

• 한국표면공학회지
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• 제36권4호
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• pp.347-355
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• 2003

Roughening of metal surfaces frequently enhances the adhesion strength of metals to polymers by mechanical interlocking. When a failure occurs at a roughened metal/polymer interface, the failure prone to be cohesive. In a previous work, an adhesion study on a roughened metal (oxidized copper-based leadframe)/polymer (Epoxy Molding Compound, EMC) interface was carried out, and the correlation between adhesion strength and failure path was investigated. In the present work, an attempt to interpret the failure path was made under the assumption that microvoids are formed in the EMC as well as near the roots of the CuO needles during compression-molding process. A simple adhesion model developed from the theory of fiber reinforcement of composite materials was introduced to explain the adhesion behavior of the oxidized copper-based leadframe/EMC interface and failure path. It is believed that this adhesion model can be used to explain the adhesion behavior of other similarly roughened metal/polymer interfaces.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2006년도 춘계학술발표회 초록집
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• pp.70-71
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• 2006

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2003년도 기술심포지움 논문집
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• pp.5-5
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• 2003

• 대한기계학회논문집
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• 제18권8호
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• pp.2158-2166
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• 1994

In order to understand the package crack emanating from the edge of leadframe after the delamination between leadframe and epoxy molding compound in an electronic packaging of surface mounting type, the M-integral and J-integral in fracture mechanics are obtained. The effects of geometry, material properties and molding process temperature on the package crack are investigated taking into account the temperature dependence of the material properties, which simulates a more realistic condition. If the temperature dependence of the material properties is considered the result of analysis conforms with observations that the crack is kinked at between 50 and 65 degree. However, in case of constant material properties at the room temperature it is found that the J-integral is underestimated and the kink crack angle is different form the observation. The effects of the material properties and molding process temperature on J-integral and crack angle are less significant that the chip size for the cases considered here. It is suggested that the geometric factors such as ship size, leadframe size are to be well designed in order to prevent(or control) the occurrence and propagation of the package crack.

• 마이크로전자및패키징학회지
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• 제11권3호
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• pp.1-7
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• 2004

주석 도금은 특정 환경하에서 위스커를 발생시키며, 이는 전자부품의 불량을 초래한다. 최근 세계곳곳에서는 환경보호를 위해 "무연"의 사용을 권고하고 있다. 본 논문에서는 두 종류 무연 도금 재료에서 도금 온도와 신뢰성시험 하에서 성장하는 위스커를 평가하였다. 도금 온도가 높아질수록 표면에 형성되는 도금 입자의 크기는 커지고, 위스커의 성장은 작아진다. 또한 온도 순환시험에서 성장한 위스커는 무광택 Sn 도금은 굽은 모양을, 무광택 Sn-Bi에서는 줄무의 모양이 관찰되었고, Sn 도금에 비해 Sn-Bi에서 위스커가 작게 성장하였다. 무광택 Sn 도금된 FeNi42 리드프레임은 TC 300 사이클에서 직경이 $7.0{\~}10.0{\mu}m$이고, 길이가 $25.0{\~}45.0{\mu}m$인 위스커가 성장하였다. 또한 Cu는 300 사이클에서는 표면에 노듈(핵 상태)만이 관찰되었고, 600 사이클에서 길이가 $3.0{\~}4.0{\mu}m$의 위스커로 성장하였다. TC 600 사이클 후 FeNi42는 계면에서 ${\~}0.34{\mu}m$의 얇은 $Ni_3Sn_4$가, Cu에서는 두께가 $0.76{\~}l.14{\mu}m$인 $Cu_6Sn_5$와 ${\~}0.27{\mu}m$의 $Cu_3Sn$ 화합물들이 두껍게 성장하였다. 따라서 FeNi42 리드프레임은 열팽창계수의 차이, Cu에서는 금속간 화합물의 형성이 위스커의 성장에 영향을 미치는 주요 인자이다.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2006년도 ISMP 2006
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• pp.21-35
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• 2006

• 대한용접접합학회:학술대회논문집
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• 대한용접접합학회 2001년도 춘계학술발표대회 개요집
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• pp.279-282
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• 2001