• 한국세라믹학회지
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• 제48권4호
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• pp.312-315
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• 2011

The effect of slurry composition and wafer flatness on a material removal rate (MRR) and resulting surface roughness which are evaluation parameters to determine the CMP characteristics of the on-axis 6H-SiC substrate were systematically investigated. 2-inch SiC wafers were fabricated from the ingot grown by a conventional physical vapor transport (PVT) method were used for this study. The SiC substrate after the CMP process using slurry added oxidizers into slurry consisted of KOH-based colloidal silica and nano-size diamond particle exhibited the significant MRR value and a fine surface without any surface damages. SiC wafers with high bow value after the CMP process exhibited large variation in surface roughness value compared to wafer with low bow value. The CMPprocessed SiC wafer having a low bow value of 1im was observed to result in the Root-mean-square height (RMS) value of 2.747 A and the mean height (Ra) value of 2.147 A.

• 마이크로전자및패키징학회지
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• 제13권3호
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• pp.47-51
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• 2006

디바이스의 고집적화로 인한 다층 배선구조로 인해 초점심도가 중요해짐에 따라 표면의 평탄도가 디바이스에 매우 큰 영향을 주게 되어, 표면의 평탄도를 결정지어주는 CMP(Chemical Mechanical Polishing) 공정이 매우 중요한 요소가 되었다. CMP 공정에는 슬러리, 연마패드, 컨디셔닝 디스크와 같은 소모품들이 사용된다. 이러한 소모품 중 하나인 컨디셔닝 디스크를 이용한 컨디셔닝 공정은 CMP 공정이 끝난 후 패드의 기공과 groove 내에 잔류 하는 화학반응물이나 슬러리와 같은 잔유물들을 컨디셔닝 디스크 표면에 부착되어 있는 다이아몬드를 이용하여 제거 함으로써 연마율을 높이고, 연마 패드의 수명을 증가 시켜주는 역할을 한다. 컨디셔닝 공정을 실시함으로써 연마 패드의 수명이 연장되기 때문에 경제적인 부분에서도 큰 이점을 가지게 된다. 본 연구에서는 이러한 CMP 공정에서 중요한 역할을 하는 소모품 중 하나인 컨디셔닝 디스크 표면에 존재하는 다이아몬드의 밀도, 형상 그리고 크기에 따라 연마 패드의 회복력 변화를 알아봄으로써 효율적인 컨디션닝 디스크의 특성을 평가해 보았다.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제53권10호
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• pp.546-550
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• 2004

Two fabrication approaches are proposed to planarize the sacrificial layer over hollow structures. One is the photoresist filling method that makes use of photolithography, thermal curing and plasma ashing. The other is the lamination method that is applying pressure and temperature to the organic film over the hollow structures. The fabrication results are compared with those of CMP process. Trenches and cavities with various dimensions have been made for the porposed process. Upon measuring the planarization levels, they are dependent on planarization methods and the geometrical size of hollow structures. The photoresist filling method is so strongly dependent on the width and depth of trenches that we have problems to use it for large dimensional trenches. To the contrary, the flatness of sacrificial layer over the trenches was found to be almost independent of trench dimensions for the lamination method. A CMP process shows the most excellent results, but the fabrication is complicated and the access to it is not so easy. It is important to choose the proper planarization method by considering the required flatness levels, materials to be planarized, and connection between the planarization step and the previous or the following process of it.

• 분석과학
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• 제32권5호
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• pp.173-184
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• 2019

As the size of semiconductors becomes smaller, it is necessary to perform high precision polishing of nanoscale. Ceria, which is generally used as an abrasive, is widely used because of its uniform quality, but its stability is not high because it has a high molecular weight and causes agglomeration and rapid precipitation. Such agglomeration and precipitation causes scratches in the polishing process. Therefore, it is important to accurately analyze the size distribution of ceria particles. In this study, a study was conducted to select dispersants useful for preventing coagulation and sedimentation of ceria. First, a dispersant was synthesized and a ceria slurry was prepared. The defoamer selection experiment was performed in order to remove the air bubbles which may occur in the production of ceria slurry. Dynamic light scattering (DLS) and asymmetrical flow field-flow fractionation (AsFlFFF) were used to determine the size distribution of ceria particles in the slurry. AsFlFFF is a technique for separating nanoparticles based on sequential elution of samples as in chromatography, and is a useful technique for determining the particle size distribution of nanoparticle samples. AsFlFFF was able to confirm the presence of a little quantities of large particles in the vicinity of 300 nm, which DLS can not detect, besides the main distribution in the range of 60-80 nm. AsFlFFF showed better accuracy and precision than DLS for particle size analysis of a little quantities of large particles such as ceria slurry treated in this study.

• 한국정보통신학회논문지
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• 제17권4호
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• pp.885-892
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• 2013

TCP/IP소켓 통신을 활용하여 데이터를 송수신하는 송수신 모델에서 데이터의 크기가 작고 데이터 전송 요청이 빈번하지 않을 경우 서버와 클라이언트 간 통신 속도의 중요성은 부각되지 않지만 오늘날 대용량 데이터에 대한 전송 요청과 빈번한 데이터 전송 요청에서 송수신 모델의 통신 속도에 대한 중요성이 부각되고 있다. 본 논문은 대용량의 데이터를 전송하는 서버의 전송 구조와 데이터를 수신하는 클라이언트의 수신 구조를 변경하여 멀티 코어(이하 CMP : ChipMulti Processor) 환경에서 데이터 전송 속도에 대한 성능향상을 기대할 수 있는 보다 효율적인 TCP/IP 송수신 모델을 제안한다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.375-375
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• 2010

CdTe as an absorber material is widely used in thin film solar cells with the heterostructure due to its almost ideal band gap energy of 1.45 eV, high photovoltaic conversion efficiency, low cost and stable performance. The deposition methods and preparation conditions for the fabrication of CdTe are very important for the achievement of high solar cell conversion efficiency. There are some rearranged reports about the deposition methods available for the preparation of CdTe thin films such as close spaced sublimation (CSS), physical vapor deposition (PVD), vacuum evaporation, vapor transport deposition (VTD), closed space vapor transport, electrodeposition, screen printing, spray pyrolysis, metalorganic chemical vapor deposition (MOCVD), and RF sputtering. The RF sputtering method for the preparation of CdTe thin films has important advantages in that the thin films can be prepared at low growth temperatures with large-area deposition suitable for mass-production. The authors reported that the optical and electrical properties of CdTe thin film were closely connected by the thickness-uniformity of the film in the previous study [1], which means that the better optical absorbance and the higher carrier concentration could be obtained in the better condition of thickness-uniformity for CdTe thin film. The thickness-uniformity could be controlled and improved by the some process parameters such as vacuum level and RF power in the sputtering process of CdTe thin films. However, there is a limitation to improve the thickness-uniformity only in the preparation process [1]. So it is necessary to introduce the external or additional method for improving the thickness-uniformity of CdTe thin film because the cell size of thin film solar cell will be enlarged. Therefore, the authors firstly applied the chemical mechanical polishing (CMP) process to improving the thickness-uniformity of CdTe thin films with a G&P POLI-450 CMP polisher [2]. CMP process is the most important process in semiconductor manufacturing processes in order to planarize the surface of the wafer even over 300 mm and to form the copper interconnects with damascene process. Some important CMP characteristics for CdTe were obtained including removal rate (RR), WIWNU%, RMS roughness, and peak-to-valley roughness [2]. With these important results, the CMP process for CdTe thin films was performed to improve the thickness-uniformity of the sputtering-deposited CdTe thin film which had the worst two thickness-uniformities of them. Some optical properties including optical transmittance and absorbance of the CdTe thin films were measured by using a UV-Visible spectrophotometer (Varian Techtron, Cary500scan) in the range of 400 - 800 nm. After CMP process, the thickness-uniformities became better than that of the best condition in the previous sputtering process of CdTe thin films. Consequently, the optical properties were directly affected by the thickness-uniformity of CdTe thin film. The absorbance of CdTe thin films was improved although the thickness of CdTe thin film was not changed.