• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.676-678
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• 2005

Future Mobile displays and the emerging systems on Glass for the upcoming TFT_LCDs or Active-OLEDs based on LTPS, and the exciting c-Si critically require very-high resolution lithography. We report the methodology and latest results on the alignment, magnification control and stitching systems on a HMA500 holographic mask aligner for printing $0.5{\mu}m-resolution$ display patterns onto glass substrates of dimensions up to $500mm{\times}400mm$.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.841-842
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• 2006

This paper has proposed a serial 8-bit DAC for column driver circuits of mobile displays using LTPS TFTs. The DAC circuit takes very small area by using parasitic capacitance of column lines as sampling and holding capacitors. Moreover, the proposed DAC does not need the analog buffer, because the DAC operation is performed on the column lines. For the data driver circuits of 2-inch qVGA OLED panel, the DAC area is $84um{\times}800um$ and the simulated DAC power consumption is 8.5mW with 10-V supply voltage.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.378-381
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• 2009

As a Joule-heat source, a conductive Mo layer was used to crystallize amorphous silicon for AMOLED backplanes. This Joule-heating induced crystallization (JIC) process could produce poly-Si having a grain size ranging from tens of nanometers to greater than several micrometers. Here, the blanket (single-shot whole-plane) crystallization could be achieved on the $2^{nd}$ and the $4^{th}$ generation glass substrate.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.140-140
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• 2010

Non-mass analyzed ion shower doping (ISD) technique with a bucket-type ion source or mass-analyzed ion implantation with a ribbon beam-type has been used for source/drain doping, for LDD (lightly-doped-drain) formation, and for channel doping in fabrication of low-temperature poly-Si thin-film transistors (LTPS-TFT's). We reported an abnormal activation behavior in boron doped poly-Si where reverse annealing, the loss of electrically active boron concentration, was found in the temperature ranges between $400^{\circ}C$ and $650^{\circ}C$ using isochronal furnace annealing. We also reported reverse annealing behavior of sequential lateral solidification (SLS) poly-Si using isothermal rapid thermal annealing (RTA). We report here the importance of implantation conditions on the dopant activation. Through-doping conditions with higher energies and doses were intentionally chosen to understand reverse annealing behavior. We observed that the implantation condition plays a critical role on dopant activation. We found a certain implantation condition with which the sheet resistance is not changed at all upon activation annealing.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.11
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• pp.900-904
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• 2011

In this paper, we investigated an anomalous hump phenomenon under the positive bias stress in p-type LTPS TFTs. The devices with inferior electrical performance also show larger hump phenomenon. which can be explained by the sub-channel induced from trapped electrons under thinner gate oxide region. We can confirm that the devices with larger hump have larger interface trap density ($D_{it}$) and grain boundary trap density ($N_{trap}$) extracted by low-high frequency capacitance method and Levinson-Proano method, respectively. From the C-V with I-V transfer characteristics, the trapped electrons causing hump seem to be generated particularly from the S/D and gate overlapped region. Based on these analysis, the major cause of an anomalous hump phenomenon under the positive bias stress in p-type poly-Si TFTs is explained by the GIDL occurring in the S/D and gate overlapped region and the traps existing in the channel edge region where the gate oxide becomes thinner, which can be inferred by the fact that the magnitude of the hump is dependent on the average trap densities.