• 전자진흥
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• 제9권9호
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• pp.34-35
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• 1989

• 전자공학회지
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• 제5권1호
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• pp.13-18
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• 1978

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2003년도 International Symposium
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• pp.103-107
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• 2003

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.98-101
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• 2002

This paper reports a parallel architecture in a HMM based speech recognition system for a low-power LSI design. The proposed architecture calculates output probability of continuous HMM (CHMM) by using concurrent and pipeline processing. They enable to reduce memory access and have high computing efficiency. The novel point is the efficient use of register arrays that reduce memory access considerably compared with any conventional method. The implemented system can achieve a real time response with lower clock in a middle size vocabulary recognition task (100-1000 words) by using this technique.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.70-73
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• 2002

High frequency digital LSI circuits are usually composed of many sub-circuits coupled with interconnects. They sometimes causes serious problems of the fault switching by time-delays, crosstalks, reflections of signals and so on. Therefore, it is very important to develop a user-friendly simulator for solving these problems. Although a moment matching method is widely used as the reduction technique of interconnects, it may happen to arise erroneous results for evaluating the poles far from the origin. In this paper, we show an asymptotic method in the complex frequency-domain, where we calculate the exact poles and residues giving large effect to the transient responses. Then, the interconnects are replaced by the asymptotic equivalent circuits using the poles and residues. Thus, we can develop a users-friendly simulator using the equivalent circuits.

• 대한기계학회논문집
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• 제6권4호
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• pp.341-345
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• 1982

The interpolator is usually built in hardware (logic circuitry), and the interpolator fabricated in a single LSI chip is recently made use of in most NC controllers, making the system more compact. However, the LSI interpolator not only has the technical difficulties but also requires high cost, in its fabrication. To solve these problems, we tried to find the method of interpolation by software, and succeeded in developing a program which, executed by INTEL's 8085 microprocessor, can distribute the input pulses of up to 4.0 [Kpps] for the linear interpolation and 3.0 [Kpps] for the circular interpolation. This paper presents the algorithm used to reduce the execution time and the flow chart of the interpolation program, and also shows the possibility of software interpolation. The interpolation program designed in assembly language is presented in the appendix.

• 한국정보보호학회:학술대회논문집
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• 한국정보보호학회 2006년도 하계학술대회
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• pp.164-168
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• 2006

전력 공격은 암호화 연산 과정 중 발생하는 소비 전력의 파형을 측정하여 비밀 정보를 알아내는 공격 방식이다. 이러한 전력 공격에 대한 취약성을 막기 위하여 message blinding, exponent blinding과 같은 기법들이 적용되어 왔다. 본 고에서는 $ECC^{[1]}$암호화 연산 과정에서, r이 임의의 정수일 때, dP=(d-r)P+rP인 관계를 이용하는 exponent blinding기법$^{[2]}$에 대하여 언급하고, 위 기법을 전력 공격의 대응책으로 적용 시 적절히 구현되지 않으면 power attack에 대하여 매우 취약하다는 것을 보인다.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 1995년도 추계학술대회 논문집
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• pp.384-387
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• 1995

Two axes lateral-shearing interferometer(LSI) specially devised for production line inspection lenses is presented. The interferometer composed with four prisms and a dove prism can test the lens performance including asymmetric aspheric lens. The dove prism which rotates the input image with respect to optical axis makes it possible. The wavefront passing through the test lens is reconstsucted by the phase derivative obtained form the two axes LSI system. Zernike-polynomials fitting of this wavefront is presented for determinating quantitative aberration of aspherical lenses.

• 한국정보관리학회:학술대회논문집
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• 한국정보관리학회 2004년도 제11회 학술대회 논문집
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• pp.163-166
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• 2004

텍스트 범주화에 관한 선행연구에서 자주 사용되면서 좋은 성능을 보인 자질 선정 기법은 문헌빈도와 카이제곱 통계량 등이다. 그러나 이들은 단어 자체가 갖고 있는 모호성은 제거하지 못한다는 단점이 있다. 본 연구에서는 kNN 분류기를 이용한 범주화 실험에서 단어간의 상호 관련성이 자동적으로 유도됨으로써 단어 자체 보다는 단어의 개념을 분석하는 잠재의미색인 기법을 자질 선정 방법으로 제안한다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
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• pp.1560-1563
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• 1987

This paper is concerned with time delay modeling of ED MOS gates which takes into account the slope of input waveform as well as the load condition. Defining the delay time as the time required to charge/discharge the load to the physical reference level, the rise/fall delay times arc derived in an explicit formula in terms of the sum of optimally weighted current unbalances at two end points of voltage transition. The proposed model is computationally effective and the error is typically within 10% of the SPICE results.