• KSCE Journal of Civil and Environmental Engineering Research
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• v.38 no.2
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• pp.349-356
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• 2018

This paper attempts to develop a connection model based on FE analysis that can be applied to the evaluation of earthquake fragility of Steel Storage Racks lacking research in Korea. In order to accomplish this goal, shaking table tests, modal tests, and various member tests (8 case, push-over test) for structural members have been conducted to understand the behavior of steel storage racks. Based on the experimental results, detailed modeling of the joints was conducted using the NX-Nastran program in order to develop a connection model for Steel storage racks to be applied to the seismic vulnerability assessment. Especially, surface to surface contact element and spring element are applied to simulate the connection between the column member and the beam member connected by the simple latch method. Spring element model developed and applied ARX (Auto Regressive eXogenous) based mathematical model. The simulation results based on the FE model showed excellent reliability with a mutual error rate of less than 8% when compared with the member test results. As a result, it was confirmed that the FE model based connection model developed in the study can be applied to the analytical model for the seismic vulnerability assessment of Steel storage racks.

• Journal of the Korean Institute of Landscape Architecture
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• v.29 no.1
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• pp.131-139
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• 2001

This paper aims at surveying through case studies the planting possibility on the interval artificial ground between the bank and the core landfill of the first section of works in the SUDOKWON Landfill area landfill area which was completed, followed by the layer-on-layer landfill process involving the latch or sealing layer against emitting landfill gas from the reclaimed waste. The survey results are as follows; 1. The layers of the artificial planting ground on the landfill were established on the basis of top-on-top procedure for a waste layer, a topping soil layer (T=50cm), a gas blocking layer (broken stones T=30cm), a filter layer (non-woven fabric 700g), a sheet protecting soil layer (T=20cm), and a blocking layer (HDPE SHEET 2.0mm), an irrigation layer (SAND T=30cm), a filter layer (non-woven fabric 700g), a sheet protecting soil layer (T=20cm), and a blocking layer (HDPE SHEET 2.0mm), an irrigation layer (SAND T=30cm), a filter layer (non-woven fabric 700g), a planting layer (T=90cm+), a top mound (T=2m). 2. Since no direct damage on the planting layer affected by the landfill gas was detected, planting is found to be still possible and successful except the severely unequal subsidence portion. 3. The mortality rate is discovered different on different trees: Pinus thunbergii (H3.0$\times$W1.0m) 11.25%, Pinus thunbergii (H2.5$\times$W0.8m) 4.73%, Koelreuteira paniculata 8.67%, Hibiscus syriacus 5.68%, Deutzia parviflora 6.50%, Forsythia koreana 8.17%, Rho. yedoense v. poukhanese 32.22%, and Spiraea pru v. symplicifolia 18.89%; although the last two of which are generally considered to have a strong generic growing character, they are subject to be weakened when exposed to the contaminated microclimate of the site like landfill gas. 4. The damage rates, on Pinus thunbergii, Koelreuteria paniculata, Hibiscus syracus, Forsythia koreana, Deutzia parviflora, Rho. yedoense v. poukhanense were shown to decrease to 7.31-17.69% in the second check (June 2000) lower than 5.77-46.92% in the first examination (June 1999), whereas the damage on Spiraea pru v. symplicifolia relatively increased. It is believed that preparatory method of the air pollution, change of temperature, odor by emitting landfill gas, and minute dust from vehicles should be made, and a research on this matter will be conducted in the near future.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.5
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• pp.25-33
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• 2011

This work proposes a skinny-type 10b 50MS/s 0.13um CMOS three-step pipeline ADC for CIS applications. Analog circuits for CIS applications commonly employ a high supply voltage to acquire a sufficiently acceptable dynamic range, while digital circuits use a low supply voltage to minimize power consumption. The proposed ADC converts analog signals in a wide-swing range to low voltage-based digital data using both of the two supply voltages. An op-amp sharing technique employed in residue amplifiers properly controls currents depending on the amplification mode of each pipeline stage, optimizes the performance of op-amps, and improves the power efficiency. In three FLASH ADCs, the number of input stages are reduced in half by the interpolation technique while each comparator consists of only a latch with low kick-back noise based on pull-down switches to separate the input nodes and output nodes. Reference circuits achieve a required settling time only with on-chip low-power drivers and digital correction logic has two kinds of level shifter depending on signal-voltage levels to be processed. The prototype ADC in a 0.13um CMOS to support 0.35um thick-gate-oxide transistors demonstrates the measured DNL and INL within 0.42LSB and 1.19LSB, respectively. The ADC shows a maximum SNDR of 55.4dB and a maximum SFDR of 68.7dB at 50MS/s, respectively. The ADC with an active die area of 0.53$mm^2$ consumes 15.6mW at 50MS/s with an analog voltage of 2.0V and two digital voltages of 2.8V ($=D_H$) and 1.2V ($=D_L$).