• Journal of the Semiconductor & Display Technology
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• v.13 no.4
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• pp.7-13
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• 2014

In this paper, an area-efficient degree-computationless modified Euclidean (DCME) algorithm is presented and implemented for high-speed Reed-Solomon (RS) decoder. The DCME algorithm can be used to solve the key equation in Reed-Solomon decoder to get the error location polynomial and the error value polynomial. A pipelined recursive structure is adopted for reducing the area of key equation solver (KES) block with sacrifice of an amount of decoding latency. For comparisons, KES block for RS(255,239,8) decoder with the proposed architecture is implemented using Verilog HDL and synthesized using Synopsys design tool and 65nm CMOS technology. The synthesis results show that the proposed architecture can be implemented with less gate counts than other existing DCME architectures.

• International Journal of Computer Science & Network Security
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• v.21 no.12spc
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• pp.451-458
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• 2021

Providing a secure and effective way to protect confidential and private data is an urgent process, and accordingly, we will present in this research paper a new method, which is called multiple rounds variable block method (MRVB) which depends on the use of a colored image that is kept secret to generate needed work and round keys. This method can be used to encrypt-decrypt data using various lengths private key and data blocks with various sizes. The number of rounds also will be variable starting from one round. MRVB will be implemented and compared with the encryption-decryption standards DES and AES to show the improvements provided by the proposed method in increasing the security level and in increasing the throughput of the process of data cryptography. The generated private key contents will depend on the used image_key and on the selected number of rounds and the selected number of bytes in each block of data.

• Journal of Power Electronics
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• v.12 no.4
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• pp.654-663
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• 2012

In this paper, a digital control strategy based on equivalent fundamental and odd harmonic resonators is proposed for single-phase DVRs. By using a delay block, which can be equivalent to a bank of resonators, it rejects the fundamental and odd harmonic disturbances effectively. The structure of the single closed-loop control system consists of a delay block, a proportional gain and a set of zero phase notch filters. The principle of the controller design is discussed in detail to ensure the stability of the system. Both the supply voltage and the load current feedforwards are used to improve the response speed and the ability to eliminate disturbances. The proposed controller is simple in terms of its structure and implementation. It has good performances in harmonic compensation and dynamic response. Experimental results from a 2kW DVR prototype confirm the validity of the design procedure and the effectiveness of the control strategy.

• The KIPS Transactions:PartC
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• v.17C no.1
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• pp.47-60
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• 2010

Randomness is a basic security evaluation item for the most cryptographic algorithms. NIST has proposed a statistical test suit for random number generators for cryptographic applications in the process of AES project. However the test suit of NIST is customized to block ciphers which have the same input and output lengths. It needs to revise NIST's test suit for key derivation functions which have multiple output blocks. In this paper we propose a revised method of NIST's statistical randomness test adequate to the most key derivation functions and some experimental results for key derivation functions of 3GSM and NIST.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.3
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• pp.35-42
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• 2007

We describe the problem of reducing the key material in the Even-Mansour cipher without security degradation. Even and Mansour proposed a block cipher based on XORing secret key material just prior to and after applying random oracle permutation P such that $C=k_2\bigoplus P(M\bigoplus k_1)$. Recently, Gentry and Ramzan showed that this scheme in the random permutation oracle can be replaced by the four-round Feistel network construction in the random function oracle and also proved that their scheme is super-pseudorandom. In this paper we reduce the key size from 2n to n, which is the optimal key size of Even-Mansour cipher in the random function oracle model and also give almost the same level of security.

• International Journal of Computer Science & Network Security
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• v.22 no.2
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• pp.209-213
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• 2022

Key exchange protocol (KEP) is an essential setup to secure authenticates transmission among two or more users in cyberspace. Digital files protected and transmitted by the encryption of the files over public channels, a single key communal concerning the channel parties and utilized for both to encrypt the files as well as decrypt the files. If entirely done, this impedes unauthorized third parties from imposing a key optimal on the authorized parties. In this article, we have suggested a new KEP term as isokey interchange protocol based on generalization of modern mathematics term as isomathematics by utilizing isonumbers for corresponding isounits over the Block Upper Triangular Isomatrices (BUTI) which is secure, feasible and extensible. We also were utilizing arithmetic operations like Isoaddition, isosubtraction, isomultiplication and isodivision from isomathematics to build iso-key interchange protocol for network communication. The execution of our protocol is for two isointegers corresponding two elements of the group of isomatrices and cryptographic performance of products eachother. We demonstrate the protection of suggested isokey interchange protocol against Brute force attacks, Menezes et al. algorithm and Climent et al. algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.6
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• pp.1075-1082
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• 2017

This paper describes a design of hash processor which can execute new hash algorithm, SHA-3 and extendable-output function (XOF), SHAKE-256. The processor that consists of padder block, round-core block and output block maximizes its performance by using the block-level pipelining scheme. The padder block formats the variable-length input data into multiple blocks and then round block generates SHA-3 message digest or SHAKE256 result for multiple blocks using on-the-fly round constant generator. The output block finally transfers the result to host processor. The hash processor that is implemented with Xilinx Virtex-5 FPGA can operate up to 220-MHz clock frequency. The estimated maximum throughput is 5.28 Gbps(giga bits per second) for SHA3-512. Because the processor supports both SHA-3 hash algorithm and SHAKE256 algorithm, it can be applicable to cryptographic areas such as data integrity, key generation and random number generation.

• Journal of Photoscience
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• v.8 no.2
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• pp.70-73
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• 2001

The chlorin-bromine building block was constructed and applied to synthesize $\delta$-bromo compounds of methyl pyropheophorbide-a. The visible spectra of the title compounds were discussed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.11
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• pp.2093-2099
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• 2016

This paper describes a design of crypto-processor that supports multiple block cipher algorithms of PRESENT, ARIA, and AES. The crypto-processor integrates three cores that are PRmo (PRESENT with mode of operation), AR_AS (ARIA_AES), and AES-16b. The PRmo core implementing 64-bit block cipher PRESENT supports key length 80-bit and 128-bit, and four modes of operation including ECB, CBC, OFB, and CTR. The AR_AS core supporting key length 128-bit and 256-bit integrates two 128-bit block ciphers ARIA and AES into a single data-path by utilizing resource sharing technique. The AES-16b core supporting key length 128-bit implements AES with a reduced data-path of 16-bit for minimizing hardware. Each crypto-core contains its own on-the-fly key scheduler, and consecutive blocks of plaintext/ciphertext can be processed without reloading key. The crypto-processor was verified by FPGA implementation. The crypto-processor implemented with a $0.18{\mu}m$ CMOS cell library occupies 54,500 gate equivalents (GEs), and it can operate with 55 MHz clock frequency.

• The Journal of Society for e-Business Studies
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• v.5 no.1
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• pp.55-73
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• 2000

Recently; EC(Electronic Commerce) is increasing with high speed based on the expansion of Internet. EC which is done on the cyber space through Internet has strong point like independence from time and space. On the contrary, it also has weak point like security problem because anybody can access easily to the system due to open network attribute of Internet. Therefore, we need the solutions that protect the security problem for safe and useful EC activity. One of these solutions is the implementation of strong cipher algorithm. NC(Nonpolynomial Complete) cipher algorithm proposed in this paper is good for the security and it overcome the limit of current 64bits cipher algorithm using 128bits key length for input, output and encryption key, Moreover, it is designed for the increase of calculation complexity and probability calculation by adapting more complex design for subkey generation regarded as one of important element effected to encryption. The result of simulation by the comparison with other cipher algorithm for capacity evaluation of proposed NC cipher algorithm is that the speed of encryption and decryption is 7.63 Mbps per block and the speed of subkey generation is 2,42 μ sec per block. So, prosed NC cipher algorithm is regarded as proper level for encryption. Furthermore, speed of subkey generation shows that NC cipher algorithm has the probability used to MAC(Message Authentication Code) and block implementation of Hash function.