• 전기의세계
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• v.28 no.6
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• pp.61-77
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• 1979

This paper is concerned with minimization process of the binary logic function. This paper describes an algorithm called the SIMPLE TABLE METHOD that well suited to minimization a switching function of any number of variables. For the Simple Table construction, a theorem based upon the numerical properties of the logic function is derived from the relationships governing minterms of the given function. Finally the minimal sum of products can be obtained in terms of the Direct Method or the Indirect Method from the table and table characteristics derived from the Simple Table. The properties and table characteristics used in this paper are described. All the minterms of a switching function are manipulated only by decimal numbers, not binary numbers. Some examples are used as a vehicle to guide the readers who are familiar with the Karnaugh map and Quine-McCluskey tabular method to this New method. These examples not only treat how to handle Don't Care miterms but also show the multiple output functions.

• The Journal of Korean Association of Computer Education
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• v.10 no.4
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• pp.17-25
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• 2007

In this paper, the simplification procedure of Karnaugh Map, which is essential to design digital logic circuits, was implemented as a web-based educational tool by Java applet. The learners can make virtual experiments on the simplification of the digital logic circuit by clicking on some buttons or filling out some text fields. The proposed simplification procedure was implemented as a Java applet which is based on the Modified Quine-McCluskey algorithm. Thus, the implemented Java applet will enable the learners to enhance the learning efficiency as a auxiliary educational tool.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.8
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• pp.1-10
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• 1995

We have analyzed the reliability of failure models in circuit-switched networks. These models are grid topology circuit-switched networks, and each node transmits a packet to a destination node using a Flooding routing method. We have assumed that the failure of each link and node is independent. We have considered two method to analyze reliability in these models : The Karnaugh Map method and joint probability method. In this two method, we have analyzed the reliability in a small grid topology circuit switched network by a joint probability method, and comared analytic results with simulated ones. For a large grid enormous. So, we have evaluated the reliability of the network by computer simulation techniques. As results, we have found that the analytic results are very close to simulated ones in a small grid topology circuit switched network. And, we have found that network reliability decreases exponentially, according to increment of link or node failure, and network reliability is almost linearly decreased according to increment of the number of links, by which call has passed. Finally, we have found an interesting result that nodes in a center of the network are superior to the other nodes from the reliability point of view.

• Korean Journal of Optics and Photonics
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• v.19 no.1
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• pp.60-67
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• 2008

An all-optical 4-bit Gray code to binary coded decimal (BCD) converter by means of commercially available numerical analysis tool (VPI) was demonstrated, for the first time to our knowledge. Circuit design approach was modified appropriately in order to fit the electrical method on an all-optical logic circuit based on a cross gain modulation (XGM) process so that signal degradation due to the non-ideal optical logic gates can be minimized. Without regenerations, Q-factor of around 4 was obtained for the most severely degraded output bit (least significant bit-LSB) with 2.5 Gbps clean input signals having 20 dB extinction ratio. While modifying the two-level simplification method and Karnaugh map method to design a Gray code to BCD converter, a general design concept was also founded (one-level simplification) in this research, not only for the Gray code to BCD converter but also for any general applications.

• Journal of the Korea Society of Computer and Information
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• v.17 no.6
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• pp.83-92
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• 2012

This paper suggests an improved method of grouping minterms based on the Decimal-Valued Matrix (DVM) method. The DVM is a novel approach to Boolean logic minimization method which was recently developed by this author. Using the minterm-based matrix layout, the method captures binary number based minterm differences in decimal number form. As a result, combinable minterms can be visually identified. Furthermore, they can be systematically processed in finding a minimized Boolean expression. Although this new matrix based approach is visual-based, the suggested method in symmetric grouping cell values can become rather messy in some cases. To alleviate this problem, the enhanced DVM method that is based on multi-level groupings of combinable minterms is presented in this paper. Overall, since the method described here provides a concise visualization of minterm groupings, it facilitates a user with more options to explore different combinable minterm groups for a given Boolean logic minimization problem.