• Journal of IKEEE
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• v.10 no.2 s.19
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• pp.149-155
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• 2006

In this study, the design of low voltage DC-DC converter with low triggering ESD (Electro-Static Discharge) protection circuit was investigated. The purpose of this paper is design optimization for low voltage(2.5V to 5.5V input range) DC-DC converter using CMOS switch. In CMOS switch environment, a dominant loss component is not switching loss but conduction loss at 1.2MHz switching frequency. In this study a constant frequency PWM converter with synchronous rectifier is used. And zener Triggered SCR device to protect the ESD phenomenon was designed. This structure reduces the trigger voltage by making the zener junction between the lateral PNP and base of lateral NPN in SCR structure. The triggering voltage was simulated to 8V.

• Bulletin of the Korean Chemical Society
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• v.35 no.8
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• pp.2415-2418
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• 2014

In this report, the contact resistance between "electrode" and "lead" is investigated for reasonable measurements of samples' resistance in a polypyrrole (PPy) nanowire device. The sample's resistance, including "electrode-lead" contact resistance, shows a decrease as force applied to the interface increases. Moreover, the sample's resistance becomes reasonably similar to, or lower than, values calculated by resistivity of PPy reported in previous studies. The decrease of electrode-lead contact resistance by increasing the applying force was analyzed by using Holm theory: the general equation of relation between contact resistance ($R_H$) of two-metal thin films and contact force ($R_H{\propto}1/\sqrt{F}$). The present investigation can guide a reliable way to minimize electrode-lead contact resistance for reasonable characterization of nanomaterials in a microelectrode device; 80% of the maximum applying force to the junction without deformation of the apparatus shows reasonable values without experimental error.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.8
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• pp.126-132
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• 1995

The electrical stress of short channel polycrystalline silicon (poly-Si) thin film transistor (TFT) has been investigated. The device characteristics of short channel poly-Si TFT with 5$\mu$m channel length has been observed to be significantly degraded such as a large shift in threshold voltage and asymmetric phenomena after the electrical stress. The dominant degradation mechanism in long channel poly-Si TFT's with 10$\mu$m and 20$\mu$m channel length respectively is charage trappling in gate oxide while that in short channel device with 5.mu.m channel length is defect creation in active poly-Si layer. We propose that the increased defect density within depletion region near drain junction due to high electric field which could be evidenced by kink effect, constitutes the important reason for this significant degradation in short channel poly-Si TFT. The proposed model is verified by comparing the amounts of the defect creation and the charge trapping from the strechout voltage.

• Transactions on Electrical and Electronic Materials
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• v.6 no.1
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• pp.1-5
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• 2005

Continued scaling of MOS devices requires the formation of the ultra shallow and very heavily doped junction. The simulation and experiment results show that the degradation of pMOS performance in logic and SRAM pMOS devices due to the excessive diffusion of the tail and a large amount of dose loss in the extension region. This problem comes from the high-temperature long-time deposition process for forming the spacer and the presence of fluorine which diffuses quickly to the $Si/SiO_{2}$ interface with boron pairing. We have studied the method to improve the pMOS performance that includes the low-energy boron implantation, spike annealing and device structure design using TCAD simulation.

• Proceedings of the KIEE Conference
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• 2002.07c
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• pp.1572-1574
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• 2002

In this paper, we discuss the electrical properties of self-assembled (2'-amino-4,4-di(ethynylp henyl)-5'-nitro-1-(thioacetyl)benzene), which has been well known as a conducting molecule having possible application to molecular level NDR device. The phenomenon of negative differential resi(NDR) is characterized by decreasing current th a junction at increasing voltage, also fabricatio MIM-type molecular electronic device and the Molecular Level Using Scanning Tunneling Microscopy.

• Progress in Superconductivity
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• v.4 no.1
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• pp.14-18
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• 2002

We had succeeded to grow bulk sing1e crystals of La／sub 2-x／Sr／sub x／$CuO_4$by the traveling solvent floating zone method (TSFZ), and to prepare La／sub 2-x／Sr／sub x／CuO$_4$single-crystalline thick films on the Zn-doped La$_2$$CuO_4$ substrate by new liquid phase epitaxial technique using an infrared heating furnace (IR-LPE). In this paper, Ireview growth of bulk single crystals and single-crystalline thick films of La／sub 2-x／Sr／sub x／$CuO_4$, and discuss on their device properties to develop high speed integrated electronic devices.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.72-72
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• 2011

Surface science is intrinsically related to the performance of solar cells. In solar cells the generation and collection of charge carriers determines their efficiency. Effective transport of charge carriers across interfaces and minimization of their recombination at surfaces and interfaces is of utmost importance. Thus, the chemistry at the surfaces and interfaces of these devices must be determined, and related to their performance. In this talk we will discuss the role of two important interfaces, First, the role of surface passivation is very important in limiting the rate of carrier of recombination. Here we will combine x-ray photoelectron spectroscopy of the surface of a Si device with electrical measurements to ascertain what factors determine the quality of a solar cell passivation. In addition, the quality of the heterojunction interface in a ZnSe/CdTe solar cell affects the output voltage of this device. X-ray photoelectron spectroscopy gives some insight into the composition of the interface, while ultraviolet photoemission yields the relative energy of the two materials' valence bands at the junction, which controls the open circuit voltage of the solar cell. The relative energies of ZnSe and CdTe at the interface is directly affected by the material quality of the interface through processing.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.13-13
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• 2011

Graphene based nano-electronic and nano-electromechanical devices will be introduced in this presentation. The first part of the presentation will be covered by our recent results on the fabrication and physical properties of artificially twisted bilayer graphene. Thanks to the recently developed contact transfer printing method, a single layer graphene sheet is stacked on various substrates/nano-structures in a controlled manner for fabricating e.g. a suspended graphene device, and single-bilayer hybrid junction. The Raman and electrical transport results of the artificially twisted bilayer indicates the decoupling of the two graphene sheets. The graphene based electromechanical devices will be presented in the second part of the presentation. Carbon nanotube based nanorelay and A new concept of non-volatile memory based on the carbon nanotube field effect transistor together with microelectromechanical switch will be briefly introduced at first. Recent progress on the graphene based nano structures of our group will be presented. The array of graphene resonators was fabricated and their mechanical resonance properties are discussed. A novel device structures using carbon nanotube field effect transistor combined with suspended graphene gate will be introduced in the end of this presentation.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.35 no.3
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• pp.268-274
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• 2007

In general, rocket or satellite circuit designers focus on reducing temperature of electronic devices in order to enhance electronic unit's reliability. This paper describes the quantitative analysis result of activation energy as well as device temperature effects to the system reliabilities. The quantitative analysis result shows that activation energy of device has more effects on system reliability than temperature does. And this paper suggests a strategy for enhancement of reliability during devices placement on PCB with simulation results.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.9
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• pp.743-751
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• 1991

This paper presents the 1.5\ulcorner PSA bipolar device which establishes the performance improvement such as the reduction of emitter resistance and substrate junction capacitance. To achieve the above electrical characteristics, RTA process and trench isolation technology were adapted. The emitter resistance and substrate capacitance of npn transistor having 1.5$[\times}6{\mu}m^{2}$emitter area was measured with 63$\Omega$and 28fF, respectively. The minimum propagation delay time shows 121ps at 0.7mW from the measurement of 31 stage ring oscillator.