• Title/Summary/Keyword: Jitter reduction

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A Study on Techniques for the Reduction of SRTS Jitter and Pointer Adjustment Jitter (SRTS 지터와 포인터 조정 지터의 감소 방식에 관한 연구)

  • Choi, Seung-Kuk
    • The KIPS Transactions:PartC
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    • v.10C no.4
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    • pp.455-462
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    • 2003
  • Techniques for the reduction of SRTS jitter and pointer adjustment jitter are studied. To reduce the stuffing jitter several methods have been proposed, such as bit leaking, stuff threshold modulation and sigma delta modulation. The characteristics of jitter generated in SRTS and pointer adjustment systen implementing these reduction techniques is analyzed with computer simulation. The results show that ms jitter value decreases to less than 50% as compared to a conventional pointer adjustment system. The amplitude of SRTS jitter using new techniques decreases or Increases dependent on system parameter.

A Study of Jitter Reduction for SDH Transmission System using Sigma-Delta Modulation

  • Han, Wook;Chang, Jin-Hyeon;Kim, Yung-Kwon
    • Journal of IKEEE
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    • v.3 no.1 s.4
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    • pp.126-132
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    • 1999
  • The SDH (Synchronous Digital Hierarchy) has been rapidly acknowledged as a world wide transmission standard replacing the existing PDH infrastructure. A bit stuffing is used for synchronization between a PDH signal and a SDH node, and a pointer justification is used for synchronization between one SDH node and the other SDH node. During above processes - a bit stuffing and a pointer processing -, a stuffing jitter and a pointer Jitter are produced and the generated jitter can cause transmission error. In this study, a stuffing jitter and a pointer jitter are modeled and analyzed. A Sigma-Delta modulation is described and an advanced jitter reduction technique using a Sigma-Delta modulation technique in the Synchronizer, Pointer Processor and Desynchronizer is provided.

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A Simple Scheme for Jitter Reduction in Phase-Differential Carrier Frequency Recovery Loop

  • Lim, Hyoung-Soo;Kwon, Dong-Seung
    • ETRI Journal
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    • v.28 no.3
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    • pp.275-281
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    • 2006
  • A very simple and efficient scheme for jitter reduction is proposed for a carrier frequency recovery loop using phase differential frequency estimation, which estimates the current frequency offset based on the difference of the average phases of two successive intervals. Analytical and numerical results presented in this paper show that by simply overlapping the observation intervals by half for frequency offset estimations, both the steady-state and transient performances can be improved. The proposed scheme does not require any additional hardware circuitry, but results in improved performance even with reduced complexity.

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Charge Pump PLL for Lock Time Improvement and Jitter Reduction (Lock Time 개선과 Jitter 감소를 위한 전하 펌프 PLL)

  • Lee, Seung-Jin;Choi, Pyung;Shin, Jang-Kyoo
    • Proceedings of the IEEK Conference
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    • 2003.07c
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    • pp.2625-2628
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    • 2003
  • Phase locked loops are widely used in many applications such as frequency synthesis, clock/data recovery and clock generation. In nearly all the PLL applications, low jitter and fast locking time is required. Without using adaptive loop filter, this paper proposes very simple method for improving locking time and jitter reduction simultaneously in charge pump PLL(CPPLL) using Daul Phase/Frequency Detector(Dual PFD). Based on the proposed scheme, the lock time is improved by 23.1%, and the jitter is reduced by 45.2% compared with typical CPPLL.

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Vibration Reduction Device for Directional Moving Satellite Antenna (지향성을 가지고 동작하는 위성 안테나 진동저감 장치 )

  • SeokWeon Choi;Sang-Soon Yong
    • Journal of Space Technology and Applications
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    • v.2 no.3
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    • pp.187-194
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    • 2022
  • Although the magnitude of the disturbance caused by the driving of the motor operated to secure the high-speed and precise directivity of the antenna is small, it acts as a major cause of impairing the image quality of the observation satellite, which requires precision directing performance. In order to acquire high-resolution image information through the improvement of the high-resolution observation satellite, proper vibration isolation and reduction design are required so that jitter generated when the directional antenna motor is driven is not transmitted to the main mission equipment. In this paper, the development process of the directional antenna vibration reduction device applied to real satellites and the effect of micro vibration reduction before and after application will be examined. This device was designed as a way to significantly improve the jitter problem by replacing only one gear in the directional antenna driving unit with a spring damper gear without any additional interface equipment. It was first applied and launched to a high-resolution earth observation satellite, and has been successfully operated so far.

Pointer Adjustment Jitter Reduction Method Using Bit Stuf fing Technique (비트 스타핑 방식을 이용한 포인터 조정 지터의 감소방법)

  • Choi Seung-Kuk
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.10 no.7
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    • pp.1196-1201
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    • 2006
  • In pointer adjustment systems, 3 byte SDH clocks are controlled for synchronization. Therefore large jitter is generated in that systems. Bit stuffing technique was introduced as method for reducing pointer adjustment jitter. However, the jitter generated in this systems is also not so small. In this paper, the problems in the bit leaking system are analyzed and new bit stuffing technique is introduced to reduce the jitter sufficiently.

A Study on Jitter Generated in STM Pointer Adjustment System (STM 포인터 조정 장치에서 발생되는 지터에 관한 연구)

  • 최승국
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.7 no.8
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    • pp.1848-1853
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    • 2003
  • Stuff threshold modulation(STM) technique is analyzed as method for reducing pointer adjustment jitter. The method for jitter reduction is described, and simulation results are presented to illustrate rms jitter performance. The results show that rms jitter value decrease to less than 50% as compared to a conventional pointer adjustment system.

Jitter Reduction by Modulator-Bias Control in Analog Fiber-Optic Links Employing a Mach-Zehnder Modulator Followed by an Erbium-Doped Fiber Amplifier (마하-젠더 광 변조기와 EDFA로 구성된 아날로그 광통신 링크에서 변조기 바이어스 조정을 이용한 랜덤 지터의 감소)

  • Lee, Min-Young;Yoon, Young-Min;Shin, Jong-Dug
    • Journal of IKEEE
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    • v.13 no.4
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    • pp.103-109
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    • 2009
  • We report an efficient jitter reduction technique in an analog fier-optic link employing a Mach-Zehnder modulator followed by an erbium-doped fiber amplifier. By adjusting the modulator-bias to $0.089V_{\pi}$, we could increase the RF gain up to 10.65 dB for 10 GHz RF signal and reduce the random jitter by 46.5%, max, at an input optical power of -0.11 dBm to the EDFA.

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Modulation Depth Dependence of Timing Jitter and Amplitude Modulation in Mode-Locked Semiconductor Lasers (모드잠김 반도체 laser의 타이밍 지터및 크기 변조의 변조 신호 크기 의존성)

  • Kim, Ji-hoon;Bae, Seong-Ju;Lee, Yong-Tak
    • Proceedings of the Optical Society of Korea Conference
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    • 2000.02a
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    • pp.276.2-278
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    • 2000
  • In a recent years, a number of approaches have been studied, including passive, active, and hybrid mode-locking of semi-conductor lasers for short pulse generation and research has been devoted to achieve low timing-jitter operation since the timing jitter is unfavorable for system applications. Among the methods of mode locking, passive mode locking does not need external rf drives, and therefore the operation and fabrication procedures are simplified. In spite of these attractive advantages of passive mode-locked laser, it has critical drawbacks such as large timing jitter and the difficulty in synchronization with external circuits. Their inherent large timing jitter value was shown to be suppressed to certain levels by means of hybrid mode-locking technique$^{(1)}$ , where the saturable absorber section was modulated by an external signal with the cavity round trip frequency. Furthermore, the subharmonic mode-locking (SHML) technique alleviates the restrictions of high speed driving electronics. It has been demonstrated experimentally$^{(1)}$ that the hybrid subharmonic mode-locking technique has lead to significant reduction of the timing jitter. (omitted)

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A Study on Bit Leaking Pointer Adjustment litter (비트 리킹 포인터 조정 지터에 관한 연구)

  • 최승국;이기영
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.8 no.6
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    • pp.1091-1095
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    • 2004
  • Bit leaking technique is analyzed as method for reducing pointer adjustment jitter. The method for jitter reduction is described, and simulation results are represented to illustrate rms jitter performance. The results show that rms jitter value decrease to less than 25% as compared to a conventional pointer adjustment system.