• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.115-121
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• 2004

GenJTAG implemented in this paper is an automatic web-based boundary scan circuit generator. GenJTAG supports all the public instructions for the boundary scan technique, and also private instructions for other DFT techniques to be applied. Users can easily edit the generated boundary scan circuit code because it is described in behavioral level with the Verilog-HDL. GenJTAG has another advantage that any one can generate the boundary scan circuit by simply accessing to the web site.

• Proceedings of the KIEE Conference
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• 1998.11b
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• pp.600-602
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• 1998

In this paper, we implement BIST to efficiently test circuits with pipeline architecture and JTAG to control implemented BIST and support board level test. Since implemented BIST is designed to be initialized using new seed, hard-to-detect faults are easily detected. Besides, to optimize area overhead, it uses JTAG instead of BIST controller and modified pipeline register instead of added test pattern generator and signature generator. And, to optimize pin overhead, it uses pins of JTAG. Function and efficiency of implemented BIST is verified by simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.85-92
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• 2004

A design of a preceding instruction decoding module(PIDM) is proposed aiming at performance enhancement of JTAG-based test complying to the IEEE 1149.1 standard. The PIDM minimizes the number of clocks by performing test access port(TAP) instruction decoding process prior to the execution of TAP-controlled test activities. The scheme allows the generation of signals such as test mode select(TMS) inside of a target system. The design employing PIDM demonstrates 15% performance enhancement with simulation of a CORDIC processor and 48% reduction of the TAP-controller's circuit size with respect to the conventional design of a non-PIDM version.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.1A
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• pp.66-72
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• 2002

In this paper, we implemented the GenJTAG, a CAD tool, which generates a code of boundary scan circuit supporing a board level testing and d BIST(Built-In Self Test) written in verilog-HDL. A boundary scan circuit code that supports user's own BIST instructions is generated based on the informations from the users. Most CAD tools hardly allow users to add their own BIST instructions because the generated code described in gate-level. But the GenJTAG generates a behavioral boundary scan circuit code so users can easily make a change on the generated code.